Method for making a chip tamper-resistant

• US 6,246,970 B1
• Filed: 07/10/1998
• Issued: 06/12/2001
• Est. Priority Date: 07/10/1998
• Status: Expired due to Term

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Silverbrook, Kia, Walmsley, Simon Robert
• Primary Examiner(s): SHAH, KAMINI S
• Application Number:
  US09/112,761
• Time in Patent Office: 1,068 Days
• Field of Search: 702/117, 702/189, 702/190, 702/191, 380/23, 380/43, 380/49, 331/78, 708/256
• US Class Current: 702/117
• CPC Class Codes: G06F 21/87 by means of encapsulation, e.g. for integrated circuits
• CPC Class Codes: G06K 19/07372 by detecting tampering with the circuit
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of detecting tampering with an integrated circuit using circuit paths extending in the integrated circuit and carrying signals which are compared to each other, and to thresholds, and providing an output signal in the event that predetermined signal conditions occur. The predetermined signal conditions which occur may be a change of state of an output of a gate which interconnects the two circuit paths, or a change of state of the output of testing circuitry which tests signals in at least one of the circuit paths against a threshold. In a further aspect the invention concerns an integrated circuit chip provided with tamper detecting circuitry.

Claims

1. An integrated circuit including tamper detecting circuitry, comprising:

a random noise generator having a first output to provide a first signal comprising a series of pseudo random bits, and a second output to provide a second signal which is related to the first signal, a first circuit path attached to the first output of the random noise generator, and a second circuit path attached to the second output of the random noise generator and at least one gate interconnecting the first and second circuit paths to produce a reset output signal which changes state if tampering causes a change to any bit of the signals in the first and second circuit paths.

2. An integrated circuit according to claim 1 where test circuitry is connected to the first and second circuit paths to test the signals in the paths and provide an output if the signals fall outside a predetermined range.

3. An integrated circuit according to claim 1 where the first and second circuit paths extend through the integrated circuit over the top of circuitry comprising the random noise generator.

4. An integrated circuit according to claim 1 where the second signal is an inverted version of the first signal, and the gate is an exclusive OR gate.

5. A method for detecting tampering with an integrated circuit, comprising the following steps:

providing a random noise generator having a first output to provide a first signal and a second output to provide a second signal, a first circuit path attached to the first output of the random noise generator, and a second circuit path attached to the second output of the random noise generator and at least one gate interconnecting the first and second circuit paths;

generating a series of pseudo random bits in the random noise generator to create a first output string of pseudo random bits at the first output and a second output string of pseudo random bits, related to the first, at the second output;

testing the output of the gate to determine whether there is a change of state.

6. A method according to claim 5, comprising the further step of resetting the integrated circuit in the event of a change of state of the output of the gate.

7. A method according to claim 5, comprising the further step of erasing secret key information in the event of a change of status of the gate.

8. A method according to claim 5, comprising the further step of testing the first and second circuit paths to test the signals in the paths and provide an output if the signals fall outside a predetermined range.

9. A method according to claim 5, where the second signal is an inverted version of the first signal, and the gate is an exclusive OR gate.