Dynamically assigning CPUs to different partitions each having an operation system instance in a shared memory space

• US 6,247,109 B1
• Filed: 06/10/1998
• Issued: 06/12/2001
• Est. Priority Date: 06/10/1998
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Kleinsorge, Frederick G., Shirron, Stephen F.
• Primary Examiner(s): FOLLANSBEE, JOHN A
• Application Number:
  US09/095,187
• Time in Patent Office: 1,098 Days
• Field of Search: 712/13, 712/228, 712/229, 711/153, 709/107, 709/108
• US Class Current: 712/13
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455

Abstract

Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. CPUs, in particular, may be migrated, or reassigned, from one operating system instance to another, allowing different loads in the system to be accommodated. The migrations involve storing the processing context of a migrating processor prior to its reassignment and, after reassignment, loading any previous processing context that it may have stored from a previous execution with the partition to which it is reassigned. Hardware flags are also provided which include an identification of which CPU belongs to which partition, and an availability indicator for each CPU, which indicates whether a given CPU is available for SMP operation.

Claims

1. A computer system having a plurality of processors, memory and I/O circuitry, the computer system comprising:

an interconnection mechanism for electrically interconnecting the processors, memory and I/O circuitry so that each processor has electrical access to all of the memory and at least some of the I/O circuitry;

a software mechanism for dividing the processors, memory and I/O circuitry into a plurality of partitions, each partition including at least one processor, some memory and some I/O circuitry;

an operating system instance running in each partition; and

a processor migration apparatus that reassigns a first processor from a first partition to a second partition, wherein said migration apparatus stores a processing context of the processor relative to the first partition prior to the reassignment.

2. A computer system according to claim 1 wherein the migration apparatus reassigns the first processor during system operation without a reboot of the entire system.

3. A computer system according to claim 1 wherein the migration apparatus initiates an indication to an operating system instance in the second partition that the first processor is available for use.

4. A computer system according to claim 1 wherein the plurality of processors is divided into groups and wherein each group comprises a console program via which an operator can interact with the processors in the group.

5. A computer system according to claim 4 wherein the migrating apparatus completes the reassignment of the migrating processor without the intervention of any of the console programs.

6. A computer system according to claim 1 wherein the software mechanism is such that each partition includes at least one CPU node that corresponds to a particular processor that is associated with a memory location in which is stored a value identifying the partition with which the processor is associated.

7. A computer system according to claim 1 further comprising a plurality of hardware flags associated with each partition, the hardware flags for a particular partition including at least one flag indicating the operational status of a particular processor executing on that partition.

8. A computer system according to claim 7 wherein the hardware flags include an availability flag indicating whether said particular processor is available to join symmetric multiprocessing (SMP) on that partition.

9. A computer system according to claim 8 wherein the availability flag is a single bit.

10. A computer system according to claim 7 wherein the each set of hardware flags include an ownership flag, and, prior to the reassignment of the first processor, a first one of the ownership flags for the first partition indicates that the first processor is under the control of an instance running on the first partition, while, after the reassignment of the first processor, the first ownership flag indicates that the first processor is no longer under the control of the instance running on the first partition.

11. A computer system according to claim 10 wherein, after the reassignment, a first ownership flag for the second partition indicates that the processor is under the control of an instance running on the second partition.

12. A computer system according to claim 1 wherein, after the reassignment of the first processor, the first processor loads any processing context that it may have stored during a previous execution with the second partition.

13. A computer system according to claim 1 wherein the migration apparatus initiates the execution of a migration instruction by the first processor.

14. A computer system having a plurality of processors, memory and I/O circuitry, the computer system comprising:

an interconnection mechanism for electrically interconnecting the processors, memory and I/O circuitry so that each processor has electrical access to all of the memory and at least some of the I/O circuitry, the plurality of processors being physically divided into groups wherein each group comprises a console program which controls the processors in the group;

a software mechanism for dividing the processors, memory and I/O circuitry into a plurality of partitions, each partition including at least one processor, some memory and some I/O circuitry, wherein a plurality of hardware flags are associated with each partition, the hardware flags for a particular partition including at least one flag indicating the operational status of a particular processor executing on that partition;

an operating system instance running in each partition; and

a processor migration apparatus that reassigns a first processor from a first partition to a second partition wherein, prior to the reassignment, said migration apparatus causes the first processor to store its current processing context with the first partition and, after the reassignement, causes the first processor to load any processing context which it may have stored from a previous execution within the second partition.

15. A method of operating a multiple processor computing system having a plurality of processors, memory and I/O circuitry, the method providing:

electrically interconnecting the processors, memory and I/O circuitry so that each processor has electrical access to all of the memory and at least some of the I/O circuitry;

using a software mechanism to divide the processors, memory and I/O circuitry into a plurality of partitions, each partition including at least one processor, some memory and some I/O circuitry;

running an operating system instance in each partition; and

reassigning a first processor from a first partition to a second partition, wherein said reassigning comprises causing, prior to the reassignment, the first processor to store a processing context relative to the first partition.

16. A method according to claim 15 wherein reassigning the first processor comprises reassigning the first processor without rebooting the entire system.

17. A method according to claim 15 further comprising maintaining configuration information indicating which of the plurality of processors is assigned to each partition.

18. A method according to claim 17 wherein the reassigning further comprises modifying the configuration information relative to the assignment of the first processor.

19. A method according to claim 15 further comprising communicating with an operating system instance in the second partition to instruct said instance to begin that the first processor is available for use.

20. A method according to claim 15 wherein the reassigning further comprises causing the first processor, after reassignment, to load any processing context which it may have stored from a previous execution with the second partition.