Apparatus and method for using checking instructions in a floating-point execution unit

• US 6,247,117 B1
• Filed: 03/08/1999
• Issued: 06/12/2001
• Est. Priority Date: 03/08/1999
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Juffa, Norbert
• Primary Examiner(s): Chan, Eddie
• Assistant Examiner(s): PATEL, GAUTAM
• Application Number:
  US09/265,230
• Time in Patent Office: 827 Days
• Field of Search: 712/222, 712/224, 712/235, 712/239, 712/228, 708/525
• US Class Current: 712/222
• CPC Class Codes: G06F 9/226 Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing

Abstract

The use of checking instructions to detect special and exceptional cases of a defined data format in a microprocessor is disclosed. Generally speaking, a checking instruction is included with the microcode of floating-point instructions to detect special and exceptional cases of operand values for the floating-point instructions. A checking instruction is configured to set one or more flags in a flags register if it detects a special or exceptional case for an operand value. A checking instruction may also set the result or results of a floating-point instruction to a result value if a special or exceptional case is detected. In addition, a checking instruction may be configured to set one or more bits in status register if a special or exceptional case is detected. After a checking instruction completes execution, a subsequent microcode instruction can be executed to determine if one or more flags were set by the checking instruction. If one or more flags have been set by the checking instruction, the subsequent microcode instruction can branch to a non-sequential microcode instruction to handle the special or exceptional case detected by the checking instruction.

Claims

1. An apparatus for executing instructions in a microprocessor, comprising:

a flag register, wherein said flag register includes a plurality of flags; and

a first execution unit coupled to said flag register, wherein said first execution unit is configured to execute a plurality of microinstructions corresponding to a floating-point instruction, wherein said floating-point instruction specifies a first operand, and wherein said first execution unit is configured to generate a first result corresponding to said floating-point instruction;

wherein said plurality of microinstructions include a checking instruction, wherein said first execution unit, in response to said checking instruction, is configured to;

(i) determine whether a first operand value of said first operand specified by said floating-point instruction corresponds to a first special or exceptional case of a defined data format; and

(ii) signal said flag register to set one or more of said plurality of flags if said first operand value corresponds to said first special or exceptional case of said defined data format.

2. The apparatus of claim 1, wherein said plurality of microinstructions includes a first microinstruction that is subsequent, in program order, to said checking instruction, and wherein said first microinstruction is configured to cause a branch to a non-sequential instruction if one or more of said flags of said flag register have been set in response to said checking instruction.

3. The apparatus of claim 2, further comprising:

an second execution unit coupled to said first execution unit, wherein said second execution unit is configured to execute said first microinstruction.

4. The apparatus of claim 3, wherein said first execution unit comprises a floating-point execution unit and wherein said second execution unit comprises an integer execution unit.

5. The apparatus of claim 1, wherein said first execution unit includes a control register, wherein said first execution unit is configured to signal said flag register to set one or more of said plurality of flags based on a mask bit of said control register if said first operand value corresponds to said first special or exceptional case of said defined data format.

6. The apparatus of claim 1, wherein said first execution unit includes a status register, wherein said first execution unit is configured to set one or more bits in said status register if said first operand value corresponds to said first special or exceptional case of said defined data format.

7. The apparatus of claim 1, wherein said floating-point instruction specifies a second operand, and wherein said first execution unit, in response to said checking instruction, is configured to:

(i) determine whether a second operand value of said second operand specified by said floating-point instruction corresponds to a second special or exceptional case of a defined data format; and

(ii) signal said flag register to set one or more of said plurality of flags if said second operand value corresponds to said second special or exceptional case of said defined data format.

8. The apparatus of claim 1, wherein said first execution unit, in response to said checking instruction, is configured to set said first result corresponding to said floating-point instruction to a first result value if said first operand value corresponds to said first special or exceptional case of said defined data format.

9. The apparatus of claim 8, wherein said first execution unit is configured to generate a second result corresponding to said floating-point instruction, and wherein said first execution unit, in response to said checking instruction, is configured to set said second result corresponding to said floating-point instruction to a second result value if said first operand value corresponds to said first special or exceptional case of said defined data format.

10. The apparatus of claim 1, wherein said first execution unit includes a plurality of floating-point execution pipelines, wherein said checking instruction is configured to execute in a first of said plurality of floating-point execution pipelines, and wherein said first of said plurality of floating-point execution pipelines is coupled to said flag register.

11. The apparatus of claim 1, further comprising:

a MROM unit coupled to said first execution unit, wherein said MROM unit is configured to store said plurality of microinstructions, and wherein said MROM unit is configured to transmit said plurality of microinstructions to said first execution unit in response to receiving said floating-point instruction;

a reorder buffer coupled to said first execution unit, wherein said reorder buffer is configured to receive said plurality of microinstructions, and wherein said reorder buffer is configured to retire said plurality of microinstructions; and

a register file coupled to said reorder buffer, wherein said register file includes said flags register;

wherein said reorder buffer is configured to update said flags register when said checking instruction is retired.

12. The apparatus of claim 1, wherein said defined data format includes an IEEE-754 format.

13. The apparatus of claim 1, wherein said defined data format includes an architecturally defined data format.

14. The apparatus of claim 1, wherein said floating-point instruction comprises an x86 instruction selected from the group consisting of:

FSCALE,

FXTRACT,

FSIN,

FCOS,

FSINCOS,

FPTAN,

FPATAN,

F2XM1,

FYL2X,

FYL2XP1,

FRNDINT,

FSTP, and

FBSTP.

15. The apparatus of claim 1, wherein said checking instruction comprises a microinstruction selected from a group consisting of:

FSCALCHK,

FXTRCHK,

FSNCSCHK,

FTANCHK,

FSINCHK,

FCOSCHK,

FL2XCHK,

FL2XP1CHK,

FATANCHK,

F2XM1CHK,

FIRNDCHK,

FSTPCHK, and

FBSTPCHK.

16. A method for executing instructions in a microprocessor, comprising:

decoding a floating-point instruction to determine whether said floating-point instruction is a microcoded instruction;

executing a plurality of microinstructions corresponding to said floating-point instruction if said floating-point instruction is a microcoded instruction;

wherein said executing said plurality of microinstructions includes;

executing a first one of said plurality of microinstructions to determine whether an operand value of an operand specified by said floating-point instruction corresponds to a special or exceptional case of a defined data format; and

wherein said executing said first one of said plurality of microinstructions includes setting one or more of a plurality of flags in a flag register if said operand value corresponds to said special or exceptional case of said defined data format.

17. The method as recited in claim 16, wherein said executing said first one of said plurality of microinstructions includes setting a result corresponding to said floating-point instruction to a result value if said operand value corresponds to said special or exceptional case of said defined data format.

18. The method as recited in claim 16, wherein said executing said plurality of microinstructions further includes:

executing a second one of said plurality of microinstructions to determine whether said one or more of said plurality of flags in said flag register was set by said first one of said plurality of microinstructions, wherein said second of said plurality of microinstructions is subsequent, in program order, to said first one of said plurality of microinstructions; and

wherein said executing said second one of said plurality of microinstructions includes;

branching to a third one of said plurality of microinstructions if one or more of said plurality of flags in said flag register was set by said first one of said plurality of microinstructions, wherein said third one of said plurality of microinstructions is non-sequential to said second one of said plurality of microinstructions.

19. The method as recited in claim 16, wherein said executing said first one of said plurality of microinstructions includes setting one or more of a plurality of flags in a flag register based upon a mask bit of a control register if said operand value corresponds to said special or exceptional case of said defined data format.

20. The method as recited in claim 16, wherein said executing said first one of said plurality of microinstructions includes setting one or more bits of a status register if said operand value corresponds to said special or exceptional case of said defined data format.

21. The method as recited in claim 16, further comprising:

executing said floating-point instruction as a fastpath instruction if said floating-point instruction is not a microcoded instruction.

22. The method as recited in claim 16, wherein said defined data format includes an IEEE-754 format.

23. The method as recited in claim 16, wherein said defined data format includes an architecturally defined data format.

24. A computer system, comprising:

a microprocessor including;

a flag register, wherein said flag register includes a plurality of flags; and

an floating-point execution unit coupled to said flag register, wherein said floating-point execution unit is configured to execute a plurality of microinstructions corresponding to a floating-point instruction, wherein said floating-point instruction specifies an operand, and wherein said floating-point execution unit is configured to generate a result corresponding to said floating-point instruction;

wherein said plurality of microinstructions include a checking instruction, wherein said floating-point execution unit, in response to said checking instruction, is configured to;

(i) determine whether an operand value of said operand specified by said floating-point instruction is a special or exceptional case of a defined data format; and

(ii) signal said flag register to set one or more of said plurality of flags if said operand value is a special or exceptional case of said defined data format;

an input/output (I/O) device coupled to said microprocessor and to another computer system, wherein said I/O device is configured to communicate between said microprocessor and said another computer system.

25. The computer system as recited in claim 24, wherein said I/O device comprises a modem.