Processor with specialized handling of repetitive operations

• US 6,247,125 B1
• Filed: 10/28/1998
• Issued: 06/12/2001
• Est. Priority Date: 10/31/1997
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Carre, Laurent, Noel-Baron, Bertrand
• Primary Examiner(s): Pan, Daniel H.
• Assistant Examiner(s): CHEN, TE Y
• Application Number:
  US09/181,795
• Time in Patent Office: 958 Days
• Field of Search: 711/138, 712/7, 712/208, 712/241, 714/30, 379/280
• US Class Current: 712/241
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter

Abstract

A processor that includes an instruction extraction stage, an instruction register, an instruction decoder, a first multiplexer that supplies the instruction register, and an autonomous counter with a presetting register. The first multiplexer receives the output of the extraction stage and the output of the instruction register, and the instruction decoder receives the output of the instruction register. Additionally, a first circuit produces a repetition signal if a received instruction is a repetition instruction, and a second circuit outputs a value from the received instruction to the presetting register when the received instruction is a repetition instruction. A third circuit produces an instruction execution signal that is supplied to the counter, and the first multiplexer is controlled so as to supply the instruction register based on a control output of the counter. The present invention also provides a method of handling instructions to be repeated by a processor.

Claims

1. A processor comprising:

an instruction extraction stage capable of receiving information from an instruction memory;

an instruction register;

a first multiplexer receiving at one input an output of the extraction stage and at another input an output of the instruction register, an output of the first multiplexer being supplied to the instruction register;

an instruction decoder receiving the output of the instruction register;

a first circuit in the instruction decoder that determines whether a received instruction is a repetition instruction, the first circuit producing a repetition signal in accordance with its determination;

an autonomous counter with a presetting register;

a second circuit that, at least when the received instruction is a repetition instruction, outputs a value contained in the received instruction to the presetting register of the counter; and

a third circuit producing an instruction execution signal that is supplied to the counter,

wherein the first multiplexer is controlled based on a control output of the counter.

2. The processor as defined in claim 1, wherein the instruction decoder also includes a fourth circuit that determines whether a received instruction is a multicycle instruction, the fourth circuit producing a multicycle signal in accordance with its determination.

3. The processor as defined in claim 2, further comprising a sequencer that receives the multicycle signal from the fourth circuit and generates a holding signal in response to the multicycle signal.

4. The processor as defined in claim 3, further comprising an OR gate that receives the control output of the counter and the holding signal of the sequencer, the OR gate generating a control signal that controls the first multiplexer.

5. The processor as defined in claim 4, further comprising:

a fifth circuit in the decoder that determines whether a received instruction is a reiteration instruction, wherein when the received instruction is a reiteration instruction, the fifth circuit outputs a value contained in the received instruction; and

a second multiplexer receiving at one input the output of the second circuit and at another input the output of the fifth circuit, the second multiplexer being controlled by the repetition signal from the first circuit.

6. The processor as defined in claim 1, further comprising a control circuit that controls the first multiplexer in accordance with the control output of the counter.

7. The processor as defined in claim 1, further comprising:

a fifth circuit in the decoder that determines whether a received instruction is a reiteration instruction,

wherein when the received instruction is a reiteration instruction, the fifth circuit outputs a value contained in the received instruction to the presetting register of the counter.

8. The processor as defined in claim 7, further comprising a second multiplexer receiving at one input the output of the second circuit and at another input the output of the fifth circuit, the second multiplexer being controlled by the repetition signal from the first circuit.

9. A processor comprising:

an instruction extraction stage;

an instruction register coupled to the instruction execution stage;

a first multiplexer receiving at one input an instruction output from the extraction stage and at another input an instruction output from the instruction register, an output of the first multiplexer being supplied to the instruction register so as to selectively feed the instruction output from the instruction register back into the instruction register;

an instruction decoder receiving the output of the instruction register;

an autonomous counter with a presetting register;

a repetition control circuit in the instruction decoder that determines whether a received instruction is a repetition instruction, wherein when the received instruction is a repetition instruction, the repetition control circuit loads a value contained in the received instruction into the presetting register of the counter; and

an execution circuit producing an instruction execution signal that is supplied to the counter,

wherein the first multiplexer is controlled by a control output of the counter.

10. The processor as defined in claim 9, further comprising a control circuit that controls the first multiplexer in accordance with the control output of the counter.

11. A method of handling instructions to be repeated by a processor, said method comprising the steps of:

loading an instruction register with an instruction;

decoding the loaded instruction to determine if it is a repetition instruction; and

if the loaded instruction is a repetition instruction;

loading an autonomous counter with a number of times the loaded instruction is to be repeated, the number being contained in the loaded instruction;

activating a counting automaton, the automaton decrementing the counter each time an instruction is executed and comparing the value of the counter with a reference value; and

feeding the loaded instruction back to the instruction register as the next instruction as long as the value of the counter is not equal to the reference value.

12. The method as defined in claim 11, further comprising the step of loading a new instruction into the instruction register when the value of the counter equals the reference value.

13. The method as defined in claim 12, further comprising the step of loading a new instruction into the instruction register after executing the loaded instruction if the loaded instruction is not a repetition instruction.