Method and apparatus for comparing real time operation of object code compatible processors

• US 6,247,144 B1
• Filed: 12/13/1994
• Issued: 06/12/2001
• Est. Priority Date: 01/31/1991
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Macias-Garza, Fernando, Miller, Todd W., McGraw, Montgomery C.
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US08/355,104
• Time in Patent Office: 2,373 Days
• Field of Search: 371/68.3, 371/16.1, 371/9.1, 371/11.3, 371/68.1, 371/67.1, 395/575, 395/183.01, 395/183.03, 395/184.01, 395/182.08, 395/182.09, 395/182.07, 364/265, 364/228.3, 364/259.2, 364/268.3, 364/268.4, 364/268.1, 364/230.3
• US Class Current: 714/25
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1683 at instruction level
• CPC Class Codes: G06F 11/1687 at event level, e.g. by interrupt or result of polling
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE

Abstract

A method and apparatus for comparing the real time operation of two object code compatible processors to discover incompatibilities and provide fault-tolerance in a computer system. The two processors run the same code and compare their write operations in real time. Logic external to the processors arbitrates between them, granting only one processor access to the system bus at any one time. The first processor executes instructions until it reaches a write or I/O data read cycle, at which time control of the system bus passes to the second processor. The second processor executes the instructions previously executed by the first processor until it catches up to the cycle pending on the first processor. If this cycle is a write cycle, then error detection logic compares the signals pending on the two processors to flag inconsistencies. If the cycle is an I/O data read cycle, the data provided to the first processor is latched to guarantee that the second processor receives the same data for its equivalent cycle. The invention includes logic circuitry which accounts for internal differences between the two processors as well as logic which allows the processors to compare their write operations while processing interrupts.

Claims

1. An apparatus for detecting inconsistencies in microprocessors in a computer system having a system bus and memory coupled to the system bus, wherein the memory includes program instructions, the apparatus comprising:

a first microprocessor coupled to the system bus for executing the instructions in the memory when said first processor has control of the system bus;

a second microprocessor coupled to the system bus for executing the instructions in the memory performed by said first processor when said second processor has control of the system bus;

processor control logic coupled to said first processor and said second processor, said processor control logic arbitrating control of the system bus between said first processor and said second processor;

wherein said processor control logic removes said first processor from control of the system bus when said first processor begins a write cycle and grants control of the system bus to said second processor;

wherein said processor control logic returns control of the system bus from said second processor to said first processor when said second processor begins said write cycle, said first processor resuming execution of the instructions in the memory; and

error detection logic coupled to said first and second processors which compares address and data information generated by each of said processors on said write cycle when said processor control logic returns control of the system bus to said first processor, said logic generating a signal indicative of a match between said address and data signals of said first and second processors.

2. The apparatus of claim 1, wherein said first and second processors include means for asserting first and second address strobe signals, respectively, when said processors begin a bus cycle, said first and second address strobe signals being coupled to said processor control logic, wherein said processor control logic further includes:

means for determining whether said bus cycle is a memory read cycle;

means for asserting third and fourth address strobe signals, respectively, to the system bus when said first and second processors begin a memory read cycle; and

means for asserting said third address strobe signal when said second processor begins a cycle other than a memory read.

3. The apparatus of claim 2, wherein said first and second microprocessors in the computer system generate HOLD requests to request control of the system bus, the apparatus further comprising:

means coupled to the system bus and to said processor control logic for receiving HOLD requests from said first and second microprocessors; and

means for asserting a hold acknowledge signal to said first and second microprocessors upon receiving said HOLD request.

4. The apparatus of claim 3, wherein said hold acknowledge signal asserting means provides said hold acknowledge signal to said processor control logic;

and

wherein said processor control logic delays assertion of said third and fourth address strobe signals while said hold acknowledge signal is asserted.

5. The apparatus of claim 4, wherein said first and second address strobe signals are provided to said HOLD request receiving means;

wherein said HOLD request receiving means delays assertion of said hold acknowledge signal when either of said address strobe signals is asserted.

6. The apparatus of claim 2, wherein each of said microprocessors in the computer system asserts a ready signal when it completes a processor bus cycle, wherein the processor control logic further includes:

means for receiving the ready signal;

means coupled to said computer system ready signal receiving means for generating third and fourth ready signals that are provided to said first and second processors, respectively;

said processor control logic including means for asserting said third ready signal after the computer system finishes a first processor bus cycle;

said processor control logic including means for asserting said fourth ready signal after the computer system finishes a second processor memory read cycle; and

said processor control logic including means for asserting said fourth ready signal after said first processor begins a cycle other than a memory read cycle and relinquishes control of the system bus.

7. The apparatus of claim 6, wherein write cycles executed by said second processor do not propagate to the system bus.

8. The apparatus of claim 1, wherein the system bus comprises a plurality of signals and said first and second processors each interface to the plurality of signals when said respective processor has control of the system bus, the apparatus further comprising:

multiplexing means coupled to said processor control logic and said first and second processors which selectively enables either said first or second processor to interface with the plurality of system bus signals at the direction of said processor control logic.

9. The apparatus of claim 8, wherein the computer system includes an input/output device coupled to the system bus and the first and second processors perform read cycles to the input/output device, wherein said first and second processors each include data pins which generate and receive data signals, wherein said processor control logic further includes:

means for removing said first processor from control of the system bus when said first processor begins an input/output data read cycle;

means for granting said second processor control of the system bus when said first processor begins said input/output data read cycle, wherein said second processor executes instructions previously performed by said first processor;

means for returning control of the system bus to said first processor when said second processor begins said input/output data read cycle;

a latching means with inputs coupled to the data pins of said first processor and outputs coupled to the data pins of said second processor, said latching means comprising;

means for latching data provided to said first processor when said first processor performs said input/output data read instruction; and

means for providing said latched data to said second processor when said second processor performs said input/output read instruction.

10. The apparatus of claim 1, wherein the computer system can generate interrupt requests to assume temporary control of the system from a current program state of the system, the apparatus further comprising:

means for providing said interrupt requests only to said first processor;

means for disabling said second processor and said error detection logic when said first processor receives said interrupt request;

means for forcing said first processor to resynchronize said first and second processors, said resynchronizing means including;

means for saving the current program state of said first processor as a saved state when first processor receives said interrupt request;

means for reinitializing said first and second processors, said reinitializing means enabling said second processor and said error detection logic; and

means for placing said first and second processors in said saved state; and

said first and second processors performing interrupt responsive operations.

11. The apparatus of claim 1, wherein said error detection logic comprises comparators which compare said address and data information generated by said first and second processors.

12. The apparatus of claim 1, wherein said first and second processors are non-identical, object code compatible processors.

13. The apparatus of claim 1, wherein said first and second processors have internal differences in the execution of certain instructions and operations, the apparatus further comprising:

internal difference logic for resynchronizing said error detection logic and said first and second microprocessors when said internal difference instructions and operations occur;

wherein said internal difference logic includes means for disabling said error detection logic during said instructions and operations.

14. The apparatus of claim 1, wherein said first processor includes an internal cache which is enabled.

15. The apparatus of claim 1, further comprising:

means coupled to said processor control logic for disabling said first processor;

wherein said processor control logic allows only said second processor access to the system bus to execute the instructions in the memory when said first processor is disabled; and

means coupled to said processor control logic for disabling said second processor;

wherein said processor control logic allows only said first processor access to the system bus to execute the instructions in the memory when said second processor is disabled.

16. A method for detecting inconsistencies in microprocessors in a computer system having a system bus, memory coupled to the system bus, wherein the memory includes program instructions, a microprocessor board having a first microprocessor coupled to the system bus for control thereof and executing the instructions in the memory when said first microprocessor has control of the system bus, a second microprocessor coupled to the system bus for control thereof and executing instructions in the memory when said second microprocessor has control of the system bus, processor control logic coupled to the first and second processors, said processor control logic arbitrating control of the system bus between the first and second processors, and error detection logic which compares write operations performed by the first and second microprocessors, the method comprising:

the first microprocessor executing instructions from the memory;

the processor control logic granting control of the system bus to the second processor when the first processor begins a write cycle, wherein said granting takes place before the write cycle is propagated to the system bus;

the second processor executing the instructions previously performed by the first microprocessor;

the processor control logic granting control of the system bus from the second processor to the first processor when the second processor begins said write cycle;

the error detection logic comparing address and data signals generated by the first and second microprocessors during said write cycle to determine inconsistent operation between the processors; and

the first processor resuming execution of the instructions from the memory.

17. The method of claim 16, further comprising:

the first and second processors asserting first and second address strobe signals, respectively, when they begin a bus cycle, said first and second address strobe signals being coupled to said processor control logic;

the processor control logic determining whether said bus cycle is a memory read cycle or a non-memory read cycle;

the processor control logic asserting third and fourth address strobe signals to the system bus when the first and second processors begin a memory read cycle; and

the processor control logic asserting said third address strobe signal when the second processor begins a cycle other than a memory read.

18. The method of claim 17, wherein the first and second microprocessors in the computer system generate HOLD requests to the microprocessor board to request control of the system bus, wherein the microprocessor board further includes a HOLD means coupled to the system bus which receives HOLD requests from the microprocessors in the computer system, the method further comprising:

the HOLD means asserting a hold acknowledge signal to the computer system and the processor control logic when the HOLD means receives a HOLD request;

the processor control logic not asserting said third and fourth address strobe signals while said hold acknowledge signal is asserted.

19. The method of claim 18, further comprising:

the first and second processor providing said first and second address strobe signals to said HOLD means; and

said HOLD means not asserting said hold acknowledge signal if either of said address strobe signals is asserted.

20. The method of claim 17, wherein each of the first and second microprocessors in the computer system asserts a ready signal when it completes a processor bus cycle, the method further comprising:

the processor control logic receiving the computer system ready signal and generating third and fourth ready signals that are provided to said first and second processors, respectively;

the processor control logic asserting said third ready signal when the first processor finishes a first processor bus cycle; and

the processor control logic asserting said fourth ready signal when the first processor begins a cycle other than a memory read and relinquishes control of the system bus.

21. The method of claim 16, wherein the computer system can generate interrupt requests and further includes a resynchronizing means, the method further comprising:

interrupt requests being provided only to the first processor;

said interrupt request disabling the second processor and the error detection logic;

the resynchronizing means saving the state of the first processor;

the resynchronizing means reinitializing the state of the first and second processors, said reinitializing enabling the second processor and the error detection logic;

the resynchronizing means placing the first and second processors in said saved state; and

the first and second processors executing the interrupt routine.

22. The method of claim 16, wherein the computer system further includes input/output memory locations which can return different data when read at different times, and latching means for storing data provided to the first processor when said first processor reads one of said input/output memory locations, the method further comprising:

the processor control logic granting control of the system bus to the second processor when the first processor begins a read cycle to one of said input/output address locations;

the second processor executing instructions previously performed by the first microprocessor;

the processor control logic returning control of the system bus to the first processor when the second processor begins a read cycle to said input/output memory location;

the first processor executing said I/O read cycle;

the latching means latching data that the first processor receives during execution of said I/O read cycle;

the processor control logic granting control of the system bus to the second processor when the first processor begins a cycle other than a memory read; and

the second processor receiving said data stored in said latching means when the second processor regains control of the system bus and executes said I/O read cycle.

23. The method of claim 16, further comprising:

the first and second microprocessors being synchronized at power on of the computer system and beginning execution in the same known state and at the same address; and

the processor control logic granting the first microprocessor control of the system bus first.

24. The method of claim 16, wherein the first and second processors are non-identical, object code compatible processors.

25. The method of claim 16, wherein the first processor includes an internal cache which is enabled.

26. The method of claim 16, wherein the first or second processors may be disabled, the method further comprising:

the processor control logic not granting control of the system bus to the processor that is disabled.

27. An apparatus for detecting inconsistencies in microprocessors in a computer system having a system bus and memory coupled to the system bus, wherein the memory includes program instructions, the apparatus comprising:

a first microprocessor coupled to the system bus for executing the instructions in the memory and for driving the system bus with signals generated by said first microprocessor when said first processor has control of the system bus;

a second microprocessor coupled to the system bus for executing the instructions in the memory normally performed by said first processor, and for driving the system bus with signals generated by said second microprocessor when said second processor has control of the system bus;

processor control logic coupled to said first processor and said second processor, said processor control logic arbitrating control of the system bus between said first processor and said second processor;

wherein said processor control logic removes said first processor from control of the system bus when said first processor begins a write cycle and grants control of the system bus to said second processor;

wherein said processor control logic returns control of the system bus from said second processor to said first processor when said second processor begins said write cycle, said first processor resuming execution of the instructions in the memory; and

error detection logic coupled to said first and second processors which compares address and data information generated by each of said processors on said write cycle when said processor control logic returns control of the system bus to said first processor, said logic generating a signal indicative of a match between said address and data signals of said first and second processors.

28. A method for detecting inconsistencies in microprocessors in a computer system having a system bus, memory coupled to the system bus, wherein the memory includes program instructions, a microprocessor board having a first microprocessor coupled to the system bus for control thereof by executing the instructions from the memory and driving the system bus with signals generated by said first microprocessor when said first microprocessor has control of the system bus, a second microprocessor coupled to the system bus for control thereof by executing instructions from the memory and driving the system bus with signals generated by said second microprocessor when said second microprocessor has control of the system bus, processor control logic coupled to the first and second processors, said processor control logic arbitrating control of the system bus between the first and second processors, and error detection logic which compares write operations performed by the first and second microprocessors, the method comprising:

the first microprocessor executing instructions from the memory;

the processor control logic granting control of the system bus to the second processor when the first processor begins a write cycle, wherein said granting takes place before the write cycle is propagated to the system bus;

the second processor executing the instructions previously performed by the first microprocessor;

the processor control logic granting control of the system bus from the second processor to the first processor when the second processor begins said write cycle;

the error detection logic comparing address and data signals generated by the first and second microprocessors during said write cycle to determine inconsistent operation between the processors; and

the first processor resuming execution of the instructions from the memory.