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Method and apparatus for comparing real time operation of object code compatible processors

  • US 6,247,144 B1
  • Filed: 12/13/1994
  • Issued: 06/12/2001
  • Est. Priority Date: 01/31/1991
  • Status: Expired due to Term
First Claim
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1. An apparatus for detecting inconsistencies in microprocessors in a computer system having a system bus and memory coupled to the system bus, wherein the memory includes program instructions, the apparatus comprising:

  • a first microprocessor coupled to the system bus for executing the instructions in the memory when said first processor has control of the system bus;

    a second microprocessor coupled to the system bus for executing the instructions in the memory performed by said first processor when said second processor has control of the system bus;

    processor control logic coupled to said first processor and said second processor, said processor control logic arbitrating control of the system bus between said first processor and said second processor;

    wherein said processor control logic removes said first processor from control of the system bus when said first processor begins a write cycle and grants control of the system bus to said second processor;

    wherein said processor control logic returns control of the system bus from said second processor to said first processor when said second processor begins said write cycle, said first processor resuming execution of the instructions in the memory; and

    error detection logic coupled to said first and second processors which compares address and data information generated by each of said processors on said write cycle when said processor control logic returns control of the system bus to said first processor, said logic generating a signal indicative of a match between said address and data signals of said first and second processors.

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