Method and apparatus for verifying that data stored in a memory has not been corrupted

• US 6,247,151 B1
• Filed: 06/30/1998
• Issued: 06/12/2001
• Est. Priority Date: 06/30/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Poisner, David I.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Chase, Shelly A
• Application Number:
  US09/107,649
• Time in Patent Office: 1,078 Days
• Field of Search: 714/719, 714/720, 714/735, 714/736, 714/819, 714/23, 714/36, 714/42, 714/734, 714/37, 365/200, 365/189.07, 365/189.08, 365/204
• US Class Current: 714/718
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 11/1497 Details of time redundant execution on a single processing unit

Abstract

An integrated circuit device includes dedicated memory verification logic to compare data read from a set of cells in a memory at a first time to data read from the same set of memory cells at a second time.

Claims

1. An integrated circuit device comprising:

dedicated memory verification logic to compare data read from a set of cells in a memory at a first time to data read from the same set of memory cells at a second time;

read control logic to read the data from the first set of cells,

wherein the memory verification logic includes

signature generation logic to perform an algorithm on the data read from the first set of cells to generate a result, and

compare logic coupled to the signature generation logic, the compare logic to compare a first result generated at the first time to a second result generated at the second time, the compare logic to produce a verify signal if the first and second results match.

2. The integrated circuit device of claim 1 wherein the algorithm is a checksum algorithm.

3. The integrated circuit of claim 1 wherein the memory includes multiple memory devices and wherein the set of cells includes cells of each of the memory devices.

4. A memory controller comprising:

memory read control logic to control reading data from selected cells in a memory; and

memory verification logic coupled to the memory read control logic, the memory verification logic to verify that data read from the selected cells at a first time matches data read from the selected cells at a second time, the memory verification logic including signature generation logic to perform a first algorithm on the data read at the first time to determine a value, the signature generation logic further to perform a second algorithm on the value and the data read at the second time, the verification logic to output a verify signal if the second algorithm produces a predetermined result.

5. A system comprising:

a bus;

a processor; and

a memory subsystem coupled to the bus and to the processor, the memory subsystem including

a first volatile memory, and

dedicated memory verification logic is configured on the first volatile memory, the dedicated memory verification logic to compare data read from a set of cells in the first volatile memory at a first time to data read from the same set of memory cells at a second time.

6. A system comprising:

a bus;

a processor; and

a memory subsystem coupled to the bus and to the processor, the memory subsystem including

a first volatile memory,

a memory controller, and

dedicated memory verification logic coupled to the first volatile memory and configured on the memory controller, the dedicated memory verification logic to compare data read from a set of cells in the first volatile memory at a first time to data read from the same set of memory cells at a second time, wherein, if the data read at the first time matches the data read at the second time, the memory controller is configured to direct the processor to execute from the first volatile memory.

7. The system of claim 6 wherein, if the data read at the first time does not match the data read at the second time, the memory controller is configured to direct the processor to execute from a second nonvolatile memory instead of from the first volatile memory.

8. A method for verifying the integrity of memory contents in a system, the method comprising:

entering the system into a suspended state; and

verifying that data read from a set of memory locations of a first memory before entering the system into a suspended state matches data read from the same set of memory locations after entering the system into the suspended state,

wherein verifying begins before a processor in the system is reset following the suspended state.

9. The method of claim 8 further including

producing a verify signal if the data read from the set of memory locations before entering the system into a suspended state matches the data read from the same set of memory locations after entering the system into the suspended state, and

directing the processor to read from the first memory instead of from a second memory responsive to the verify signal.