Incremental method for critical area and critical region computation of via blocks

• US 6,247,853 B1
• Filed: 05/26/1998
• Issued: 06/19/2001
• Est. Priority Date: 05/26/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Lavin, Mark Alan, Papadopoulou, Evanthia, Tellez, Gustavo Enrique, Allen, Archibald John
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US09/085,093
• Time in Patent Office: 1,120 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 395/500.05, 395/500.06, 395/500.2
• US Class Current: 716/52
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

An efficient computer implemented method computes critical area for via blocks in Very Large Scale Integrated (VLSI) circuits. The method is incremental and takes advantage of the hierarchy in the design. In order to increase the efficiency further we use the L_∞ or the L₁ metric instead of the Euclidean geometry.

Claims

1. A computer implemented method for critical area computation of via blocks in VLSI circuits comprising the steps of:

a) retrieving a design layer containing a plurality of via shapes;

b) retrieving a list of defect sizes ordered in increasing size;

c) identifying all of said vias as critical vias or as non-critical vias, critical vias being smaller than a size determined by a minimum defect size;

d) generating critical region for said critical vias;

e) identifying all vias from said non-critical vias being smaller than a size determined by a next smallest defect size as critical vias;

f) generating critical region for each said identified critical vias; and

g) repeating steps (d) and (e) for each defect size in said list.

2. The computer implemented method of claim 1 wherein the step (f) of generating the critical region comprises:

1) expanding said critical region by the difference between a radius of each said defect and the next smallest defect size; and

2) introducing new critical regions for those critical vias identified in step (e).

3. The computer implemented method of claim 2 wherein the step (a) of retrieving a design layer further comprises replacing redundant vias with a minimum enclosing rectangle.

4. The computer implemented method of claim 2 wherein the step (f) of generating critical regions for critical vias having a critical radius r_i comprises the following steps:

1) Expanding the critical region CR<sub>i−

1</sub> by dr=r_i−

r<sub>i−

1</sub>;

2) Computing for those vias with a critical radius between r_i and r<sub>i−

1</sub>, a collection of new polygonal critical regions, CR_new;

3) Unioning CR_new and the expanded critical region CR<sub>i−

1</sub> as Cr_i; and

4) computing the area of CR_i.

5. The computer implemented method of claim 4 wherein the defects are assumed to be square.

6. The computer implemented method of claim 4 wherein the defects are assumed to be circular.

7. The computer implemented method of claim 4 wherein the defects are assumed to be square diamond shaped.

8. The computer implemented method of claim 2 wherein the step (f) of generating critical regions for critical vias having a critical radius r_i comprises the following steps:

1) Expanding the critical region CR<sub>i−

1</sub> by dr=r_i−

r<sub>i−

1</sub>;

2) Computing for those vias with r_i+1>

{circumflex over (r)}_i, a collection of new polygonal critical regions, CR_new;

3) Computing for non-square vias with {circumflex over (r)}₀≦

r_i<

{circumflex over (r)}₁, a collection of polygonal critical regions, CRd_i;

4) Unioning CR_new and the expanded critical region CR<sub>i−

1</sub> as Cr_i; and

5) Unioning CR_i and CRd_i and computing therefrom an area of the unioned shapes.

9. The computer implemented method of claim 8 wherein the defects are assumed to be octagonal shaped.

10. A method of integrated circuit chip design including checking a chip design according to the computer implemented method of claim 1 and further comprising the step of:

h) modifying a design layer of said checked chip design based on said generated actual critical region to improve manufacturing yield; and

i) rechecking said chip design using said computer implemented method.

11. A method of integrated circuit chip design according to claim 10 further comprising repeating steps (h) and (i) until a desired predicted yield is achieved.

12. A system for analyzing defect critical areas of integrated circuit chips, said system comprising:

means for storing a plurality of design shapes on a design layer;

means for determining critical regions for said stored design shapes;

means for organizing said determined critical regions according to a critical radius; and

means for generating an actual critical region for each remaining said seed critical region.

13. A system for analyzing defect critical areas integrated circuit chips as in claim 12, further comprising means for expanding identified critical regions according to the difference between a critical radius of said identified critical region and the radius of said minimum defect size.

14. A system for analyzing defect critical areas integrated circuit chips as in claim 12, further comprising means for determining a least critical shape.