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Incremental method for critical area and critical region computation of via blocks

  • US 6,247,853 B1
  • Filed: 05/26/1998
  • Issued: 06/19/2001
  • Est. Priority Date: 05/26/1998
  • Status: Expired due to Term
First Claim
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1. A computer implemented method for critical area computation of via blocks in VLSI circuits comprising the steps of:

  • a) retrieving a design layer containing a plurality of via shapes;

    b) retrieving a list of defect sizes ordered in increasing size;

    c) identifying all of said vias as critical vias or as non-critical vias, critical vias being smaller than a size determined by a minimum defect size;

    d) generating critical region for said critical vias;

    e) identifying all vias from said non-critical vias being smaller than a size determined by a next smallest defect size as critical vias;

    f) generating critical region for each said identified critical vias; and

    g) repeating steps (d) and (e) for each defect size in said list.

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