Method of fabricating a self-aligned contact

• US 6,248,643 B1
• Filed: 04/02/1999
• Issued: 06/19/2001
• Est. Priority Date: 04/02/1999
• Status: Expired due to Term

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Sheu, Bor-Ru, Yang, Fu-Liang, Jeng, Erik S., Hsieh, Chien-Sheng, Lin, Wei-Ray
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Smoot, Stephen W.
• Application Number:
  US09/285,534
• Time in Patent Office: 809 Days
• Field of Search: 438/221, 438/224, 438/253, 438/675, 438/424, 438/299, 438/197, 438/218
• US Class Current: 438/424
• CPC Class Codes: H01L 21/32053 of metal-silicide layers
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A method for fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level. The process begins by successively forming a gate oxide layer and a first gate electrode layer on a silicon substrate. Next, fully planarized trench isolation regions are formed using sacrificial oxide and nitride layers and selective etching. A sacrificial pad oxide layer and a first sacrificial nitride layer are formed. The first sacrificial nitride layer, the sacrificial pad oxide layer, the first gate electrode layer, the gate oxide layer, and the silicon substrate are patterned to form trenches. A fill oxide layer is deposited in the trenches and over the first sacrificial nitride layer. An oxide etch is performed which recesses the fill oxide layer in the trenches below the level of the top of the first nitride layer. A second sacrificial nitride layer is formed on the fill oxide layer and over the first sacrificial nitride layer. Chemical-mechanical polishing is performed. Successive oxide etch, nitride etch and oxide etch steps are performed defining elevated trench isolation regions fully planarized with the first gate electrode layer. A silicide layer, a dielectric layer and a top nitride layer are formed. The top nitride layer, the dielectric layer, the silicide layer, the first gate electrode layer and the gate oxide layer are patterned forming gate structures between elevated trench isolation regions and conductive lines on elevated trench isolation regions. Spacers are formed on the sidewalls of the gate structures, the conductive lines and the elevated trench isolation regions. Then, self-aligned contact plugs are formed adjacent to the spacers.

Claims

1. A method of fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level comprising the steps of:

a. providing a semiconductor substrate having elevated trench isolation regions dividing and defining active areas there between;

said substrate having thereon a gate oxide layer in said active areas;

said gate oxide layer having thereon a first gate electrode layer;

wherein said elevated trench isolation regions are formed coplanar to said gate electrode layer by forming sequential sacrificial oxide, nitride, oxide, and nitride layer and performing sequential chemical-mechanical polishing, selective oxide, selective nitride and timed oxide etches;

b. forming a silicide layer on said first gate electrode layer and on said elevated trench isolation regions;

said silicide layer being planar with uniform thickness;

c. forming a dielectric layer on said silicide layer;

said dielectric layer being planar with uniform thickness;

d. forming a top nitride layer on said dielectric layer;

said nitride layer being planar with uniform thickness;

e. patterning said top nitride layer, said dielectric layer, said silicide layer, said first gate electrode layer and said gate oxide layer using photolithography;

thereby forming gate structures with sidewalls between said elevated trench isolation regions and conductive lines with sidewalls on said elevated trench isolation regions;

said elevated trench isolation regions having sidewalls;

whereby said substrate is exposed adjacent to said gate structures;

said photolithography being performed on a fully planar surface;

f. forming spacers on said sidewalls of said gate structures, said conductive lines and said elevated trench isolation regions; and

g. selectively forming contact plugs on said substrate adjacent to said spacers.

2. The method of claim 1 wherein said first gate electrode layer has a thickness between 800 Å

and 1500 Å

.

3. The method of claim 1 wherein said silicide layer is composed of Tungsten Silicide.

4. The method of claim 1 wherein said contact plugs are composed of epitaxial silicon.

5. The method of claim 1 wherein said contact plugs are composed of Tungsten.

6. A method of fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level consisting of the steps of:

a. forming a gate oxide layer on a silicon substrate;

b. forming a first gate electrode layer on said gate oxide layer;

c. forming a sacrificial pad oxide layer on said first gate electrode layer;

d. forming a first sacrificial nitride layer on said sacrificial pad oxide layer;

e. patterning said first sacrificial nitride layer, said sacrificial pad oxide layer, said first gate electrode layer, said gate oxide layer, and said silicon substrate to form trenches;

f. forming a fill oxide layer in said trenches and over said first sacrificial nitride layer;

g. performing an oxide etch;

whereby said fill oxide layer in said trenches is recessed below the level of the top of said first nitride layer;

h. forming a second sacrificial nitride layer on said fill oxide layer and over said first sacrificial nitride layer;

i. performing chemical-mechanical polishing on said second sacrificial nitride layer, said fill oxide layer, and said first sacrificial nitride layer stopping on said second sacrificial nitride layer in said trenches;

j. performing an oxide etch;

whereby the portions of said fill oxide layer not in said trenches are removed;

k. performing a nitride etch;

whereby the first sacrificial nitride layer and the second sacrificial nitride layer are removed;

l. performing an oxide etch;

whereby the sacrificial pad oxide layer is removed and elevated trench isolation regions are defined;

m. forming a silicide layer on said first gate electrode layer and on said elevated trench isolation regions;

n. forming a dielectric layer on said silicide layer;

o. forming a top nitride layer on said dielectric layer;

p. patterning said top nitride layer, said dielectric layer, said silicide layer, said first gate electrode layer and said gate oxide layer;

thereby forming gate structures with sidewalls between said elevated trench isolation regions and conductive lines with sidewalls on said elevated trench isolation regions;

said trench isolation regions having sidewalls;

whereby said substrate is exposed adjacent to said gate structures;

q. forming a dielectric spacer layer over said top nitride layer;

r. etching said spacer layer to form spacers on said sidewalls of said gate structures, said conductive lines and said elevated trench isolation regions; and

s. selectively forming contact plugs on said substrate adjacent to said spacers.

7. The method of claim 6 wherein said first gate electrode layer has a thickness of between about 800 Å

and 1500 Å

.

8. The method of claim 6 wherein said sacrificial pad oxide layer has a thickness of between about 50 Å

and 200 Å

.

9. The method of claim 6 wherein said first sacrificial silicon nitride layer has a thickness of between about 1800 Å

and 2200 Å

.

10. The method of claim 6 wherein said trench extends into said substrate a depth of between 3000 Å

and 6000 Å

.

11. The method of claim 6 wherein, following the first oxide etch, said fill oxide layer is recessed to a depth of between 1000 Å

and 1500 Å

below the level of the top of said first sacrificial nitride layer.

12. The method of claim 6 wherein said second sacrificial nitride layer has a thickness between 500 Å

and 800 Å

.

13. The method of claim 6 wherein said oxide etch steps use a buffered oxide etch (BOE) process and said nitride etch is peformed using a hot H₃PO₄dip.

14. The method of claim 6 wherein said silicide layer is composed of Tungsten Silicide.

15. The method of claim 6 wherein said contact plugs are composed of epitaxial silicon.

16. The method of claim 6 wherein said contact plugs are composed of Tungsten.