Sequential correlated double sampling technique for CMOS area array sensors

• US 6,248,991 B1
• Filed: 12/30/1998
• Issued: 06/19/2001
• Est. Priority Date: 12/31/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Dierschke, Eugene G., Chen, Zhiliang Julian
• Primary Examiner(s): Lee, John R.
• Application Number:
  US09/223,165
• Time in Patent Office: 902 Days
• Field of Search: 250/208.1, 250/214.R, 250/214.A, 250/214.1, 327/94, 327/95, 348/241, 348/300, 348/301, 348/308, 257/290, 257/291, 257/292, 257/293
• US Class Current: 250/208.1
• CPC Class Codes: H04N 2209/00 Details of colour television systems
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A CMOS area array sensor with reduced fixed pattern noise. Device threshold voltage variations are minimied using a Sequential Correlated Double Sampling technique in a column circuitry.

Claims

1. A pixel-sensing MOS integrated circuit, comprising:

an array of pixel circuits each performing an illumination-sensing operation to provide a pixel signal;

a plurality of column amplifying circuits each connected to read said pixel circuits from a column of said array;

wherein said column amplifying circuit performs a correlated double sampling operation on said pixel signals from said column through a single path, and comprises at least one storage device for cancelling variations of said pixel signals; and

an output circuit.

2. The integrated circuit of claim 1, wherein said pixel circuits are of an active-pixel architecture.

3. The integrated circuit of claim 1, wherein said amplifying circuit comprises a PMOS transistor.

4. The integrated circuit of claim 1, wherein said amplifying circuit comprises an operational amplifier.

5. The integrated circuit of claim 1, wherein said storage device is a capacitor.

6. The integrated circuit of claim 1, wherein said amplifying circuit reads said pixel circuits individually.

7. The integrated circuit of claim 1, wherein said variations comprise pixel-sensing transistor threshold voltages variations, and column amplifier variations.

8. The integrated circuit of claim 1, wherein a reset voltage, and a photodiode voltage is read from said pixel circuit.

9. The integrated circuit of claim 1, wherein said output circuit comprises a PMOS transistor.

10. A pixel-sensing MOS integrated circuit, comprising:

an array of pixel circuits each performing an illumination-sensing operation to provide a pixel signal;

a column amplifying switching means connected to read said pixel circuits in a column of said array;

wherein said column amplifying switching means is configured to clock signal and noise levels from said pixel circuits of said column through a single path to perform cancellation of circuit variations, and performs a correlated double sampling operation; and

an output circuit.

11. The integrated circuit of claim 10, wherein said pixel circuits are of an active-pixel architecture.

12. The integrated circuit of claim 10, wherein said amplifying switching means comprises a PMOS transistor.

13. The integrated circuit of claim 10, wherein said amplifying switching means comprises an operational amplifier.

14. The integrated circuit of claim 10, wherein said storage devices are capacitors.

15. The integrated circuit of claim 10, wherein said amplifying switching means reads said pixel circuits individually.

16. The integrated circuit of claim 10, wherein said amplifying switching means reads a column of said pixel circuits individually.

17. The integrated circuit of claim 10, wherein said cancelled variations comprise pixel-sensing transistor threshold voltages variations, and column amplifier variations.

18. The integrated circuit of claim 10, wherein said read operation comprises first, a reset voltage, and second, a photodiode voltage.

19. The integrated circuit of claim 10, wherein said output circuit comprises a PMOS transistor.

20. A pixel-sensing MOS integrated circuit, comprising:

one of a plurality of pixel circuits providing a signal having a voltage, each pixel circuit comprising a sensing transistor;

a column selecting circuit comprising an amplifying transistor;

wherein said column selecting circuit sequentially connects to ones of said pixel circuits to perform correlated double sampling on said signal voltage by reading first and second voltages therefrom;

wherein said column selecting circuit comprises first and second storage devices;

wherein the effects from threshold voltage mismatches of both said sensing transistor and said column transistor are minimized; and

an output driver circuit coupled to said column selecting circuit and providing the difference in said voltages at an output terminal;

whereby fixed pattern noise is substantially minimized.

21. The integrated circuit of claim 20, wherein said amplifying transistor is a PMOS transistor.

22. The integrated circuit of claim 20, wherein said storage devices are capacitors.

23. The integrated circuit of claim 20, wherein said column selecting circuit reads said pixel circuits individually.

24. The integrated circuit of claim 20, wherein said column selecting circuit reads a column of said pixel circuits individually in sequence.

25. The integrated circuit of claim 20, wherein said first voltage is a reset voltage, and said second voltage is a photodiode voltage.

26. The integrated circuit of claim 20, wherein said output circuit comprises a PMOS transistor.

27. A photosensing imaging system, comprising:

an imager, comprising

a focusing element,

a pixel-sensing MOS integrated circuit imager receiving light from said focusing element, and comprising,

an array of pixel circuits each performing an illumination-sensing operation to provide a pixel signal,

a plurality of column amplifying circuits each connected to read said pixel circuits from a column of said array;

wherein said column amplifying circuit performs a correlated double sampling operation on said pixel signals through a single path and providing resultant pixel data, and comprises at least one storage device for canceling variations of said pixel signals, and

an output circuit;

a processor connected to control said imager; and

a storage medium for receiving and storing said pixel data from said imager.

28. The system of claim 27, wherein said pixel circuits are of an active-pixel architecture.

29. The system of claim 27, wherein said pixel circuits are of a passive-pixel architecture.

30. The system of claim 27, wherein said storage device is a capacitor.

31. The system of claim 27, wherein said column amplifying circuits each read said pixel circuits individually.

32. The system of claim 27, wherein said column amplifying circuits each read a column of said pixel circuits individually.

33. A low-noise method of sampling pixel circuits, each pixel circuit providing a signal having a voltage, said pixel circuits being arranged in columns in a CMOS area array sensor, comprising the steps of:

(a.) receiving a first voltage at a first node of said pixel circuit, wherein said first voltage is generated by a photosensitive circuit and received at a control terminal of a first active device that communicates said first voltage to a second terminal of said first active device;

(b.) initializing said a column circuit associated with a column of pixel circuits and an output circuit in preparation for reading said pixel circuits, wherein said column circuit comprises first and second storage circuits, and a second active device for amplifying a signal applied thereto and providing an amplified signal as an output signal of said column circuit, wherein said first and second storage circuits cooperate with said first and second active devices to modify said output signal of said column circuit in accordance with voltages stored on said first and second storage circuits;

(c.) reading into said column circuit, said first voltage at said second terminal of said first active device of a selected pixel in said column, wherein the voltage on said first storage circuit rises to a first level, and storing a compensation voltage on said second storage circuit;

(d.) stabilizing said first and second storage circuits in preparation for reading a second voltage into said column circuit;

(e.) reading a second voltage from said selected pixel circuit and amplifying said second voltage to obtain an output signal of said column circuit whereby through the cooperation of said first and second storage circuits said step of reading and amplifying substantially subtracts out from said column circuit output signal threshold voltage variations between said first and second active devices; and

(f.) transferring said column circuit output signal to an output node of said output circuit;

whereby said sampling method is performed in no more than 5 clocking cycles.

34. The method of claim 33, wherein said pixel circuit is an active pixel circuit.

35. A low-noise method of sampling pixel and column circuits in a CMOS area array sensor, comprising the steps of:

(a.) reading a pixel signal from a pixel circuit;

(b.) reading a noise signal from said pixel circuit; and

(c.) sequentially offsetting said pixel signal with said noise signal in a capacitor to minimize device variations and noise.

36. The method of claim 35, wherein step (a.) is performed before step (b.).

37. The method of claim 35, wherein step (b.) is performed before step (a.).