Hydrogen barrier encapsulation techniques for the control of hydrogen induced degradation of ferroelectric capacitors in conjunction with multilevel metal processing for non-volatile integrated circuit memory devices

• US 6,249,014 B1
• Filed: 10/01/1998
• Issued: 06/19/2001
• Est. Priority Date: 10/01/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Ramtron International Corporation (Infineon Technologies AG)
• Inventors: Bailey, Richard A.
• Primary Examiner(s): Lee, Eddie C.
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/164,952
• Time in Patent Office: 992 Days
• Field of Search: 257/295, 257/296, 257/306, 257/310
• US Class Current: 257/295
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A hydrogen barrier encapsulation technique for the control of hydrogen induced degradation of ferroelectric capacitors in non-volatile integrated circuit memory devices. The resultant device structure ameliorates the hydrogen induced degradation of ferroelectric capacitors by completely encapsulating the capacitor within a suitable hydrogen barrier material, such as chemical vapor deposition (“CVD”) or sputtered silicon nitride, thus ensuring process compatibility with industry standard process steps. Although the deposition process for CVD Si₃N₄ itself contains hydrogen, the deposition time may be kept relatively short thereby allowing the TiN local interconnect layer to act as a “short term” hydrogen barrier. The techniques of the present invention are applicable to all known ferroelectric dielectrics including Perovskites and layered Perovskites (whether doped or undoped) including PZT, PLZT, BST, SBT and others while simultaneously allowing for a potentially broader choice of electrode materials and the use of a forming gas anneal process step on the completed IC structure.

Claims

1. A memory device comprising:

a bottom electrode overlying an insulating layer;

a dielectric layer overlying said bottom electrode;

a top electrode overlying said dielectric layer;

a second insulating layer overlying said top electrode;

a contact extending through an opening in the second insulating layer providing electrical coupling to said top electrode; and

a layer of hydrogen barrier material formed on an upper surface of said contact adjacent said opening in the second insulating layer.

2. The memory device of claim 1 wherein said hydrogen barrier material comprises silicon nitride.

3. The memory device of claim 1 wherein said hydrogen barrier material comprises TiO₂.

4. The memory device of claim 1 wherein said hydrogen barrier material comprises a ferroelectric material.

5. The memory device of claim 1 wherein said hydrogen barrier material comprises lead zirconium titanate.

6. The memory device of claim 1 wherein said hydrogen barrier material comprises alumina.

7. The memory device of claim 1 wherein said hydrogen barrier material is substantially 200 Å

-2000 Å

in thickness.

8. The memory device of claim 1 wherein said contact comprises TiN.

9. The memory device of claim 1 wherein said bottom electrode is selected from a group comprising titanium, iridium, ruthenium and platinum.

10. The memory device of claim 1 wherein said top electrode is selected from a group comprising titanium, iridium, ruthenium and platinum.

11. The memory device of claim 1 wherein said dielectric layer is selected from a group comprising Perovskites and layered Perovskites.

12. The memory device of claim 1 further comprising an additional hydrogen barrier material layer interposed between said bottom electrode and said insulating layer and substantially surrounding said bottom electrode, end portions of said dielectric layer and end portions of said top electrode, and further interposed between said second insulating layer and said top electrode to abut said contact.

28. The memory device of claim 1, wherein the layer of hydrogen barrier material is formed on said contact overlying substantially all of the contact upper surfaces.

29. The memory device of claim 28, further including a second contact extending through a second opening in the second insulting layer providing electrical coupling to the bottom electrode and a second layer of hydrogen barrier material formed on an upper surface of the second contact adjacent the second opening in the second insulating layer.

13. An integrated circuit device including at least one capacitor integrated thereon, said device comprising:

a substrate having a major surface thereof;

a first hydrogen barrier material layer overlying said substrate;

a first insulating layer overlying said first hydrogen barrier material layer;

a first electrode layer overlying said first insulating layer and substantially coextensive therewith;

a dielectric layer overlying said first insulating layer;

a second electrode layer overlying said dielectric layer;

a contact electrically adjoining said second electrode layer at an upper surface thereof;

a second insulating layer overlying exposed portions of said first electrode layer, said dielectric layer and said second electrode layer adjacent said contact;

a second hydrogen barrier material layer contiguous with said first hydrogen barrier material layer and overlying said second insulating layer; and

an additional hydrogen barrier material layer overlying said contact.

14. The integrated circuit device of claim 13 wherein said first, second and additional hydrogen barrier material layers are selected from a group comprising silicon nitride, lead zirconium titanate and alumina.

15. The integrated circuit device of claim 13 wherein said first hydrogen barrier layer is substantially 500 Å

in thickness.

16. The integrated circuit device of claim 13 wherein said second hydrogen barrier layer is substantially 80 Å

in thickness.

17. The integrated circuit device of claim 13 wherein said additional hydrogen barrier layer is substantially between 200 Å

-2000 Å

in thickness.

18. The integrated circuit device of claim 13 wherein said first and second insulating layers comprise UTEOS.

19. The integrated circuit device of claim 13 wherein said first insulating layer is substantially 500 Å

in thickness.

20. The integrated circuit device of claim 13 wherein said second insulating layer is substantially 5000 Å

in thickness.

21. The integrated circuit device of claim 13 wherein said first and second electrodes are formed from a group comprising iridium, ruthenium, platinum and titanium.

22. The integrated circuit device of claim 13 wherein said first electrode comprises substantially 200 Å

of titanium and 1500 Å

of platinum.

23. The integrated circuit device of claim 13 wherein said second electrode comprises substantially 1500 Å

of platinum.

24. The integrated circuit device of claim 13 wherein said dielectric layer is selected from a group comprising Perovskites and layered Perovskites.

25. The integrated circuit device of claim 13 wherein said dielectric layer is substantially 500 Å

-2400 Å

in thickness.

26. The integrated circuit device of claim 13 wherein said contact comprises TiN.

27. the integrated circuit device of claim 13 wherein said contact forms a portion of a local interconnect on said integrated circuit device.