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Device method for enhanced avalanche SOI CMOS

  • US 6,249,029 B1
  • Filed: 05/26/1999
  • Issued: 06/19/2001
  • Est. Priority Date: 09/23/1998
  • Status: Expired due to Fees
First Claim
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1. A method of fabricating a field effect transistor in a substrate with a source, drain and gate, wherein the field effect transistor has an electrically floating body and is substantially electrically isolated from the substrate, comprising:

  • implanting a relatively high dose halo implant in a portion of a drain edge region at a gate boundary to enhance the avalanche multiplication current through the device from the drain to said floating body, and;

    providing a high resistance path between the floating body of the field effect transistor and the source of the field effect transistor, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current.

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