Device method for enhanced avalanche SOI CMOS
First Claim
1. A method of fabricating a field effect transistor in a substrate with a source, drain and gate, wherein the field effect transistor has an electrically floating body and is substantially electrically isolated from the substrate, comprising:
- implanting a relatively high dose halo implant in a portion of a drain edge region at a gate boundary to enhance the avalanche multiplication current through the device from the drain to said floating body, and;
providing a high resistance path between the floating body of the field effect transistor and the source of the field effect transistor, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current.
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Abstract
A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.
50 Citations
10 Claims
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1. A method of fabricating a field effect transistor in a substrate with a source, drain and gate, wherein the field effect transistor has an electrically floating body and is substantially electrically isolated from the substrate, comprising:
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implanting a relatively high dose halo implant in a portion of a drain edge region at a gate boundary to enhance the avalanche multiplication current through the device from the drain to said floating body, and;
providing a high resistance path between the floating body of the field effect transistor and the source of the field effect transistor, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification