Self-encapsulated copper metallization

• US 6,249,055 B1
• Filed: 02/03/1998
• Issued: 06/19/2001
• Est. Priority Date: 02/03/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dubin, Valery
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): VU, HUNG K
• Application Number:
  US09/017,676
• Time in Patent Office: 1,232 Days
• Field of Search: 257/751, 257/752, 257/758, 257/762, 257/763, 257/765, 257/767, 257/771, 257/774, 438/622, 438/626, 438/627
• US Class Current: 257/758
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 23/53233 Copper alloys
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Copper or copper alloy interconnection patterns are formed by a damascene technique. An aluminum or magnesium alloy is deposited in a damascene opening formed in a dielectric layer. Copper or a copper alloy is then electroplated or electroless plated on the aluminum or magnesium alloy, filling the opening. During low temperature annealing, aluminum or magnesium atoms diffuse through the copper or copper alloy layer and accumulate on its surface forming a self-encapsulated oxide to prevent corrosion and diffusion of copper atoms.

Claims

1. A semiconductor device having an interconnection pattern comprising:

a dielectric layer having an opening therein; and

a composite metal layer inlaid in the opening, the composite metal layer comprising;

a metal layer comprising a magnesium alloy lining the entire opening;

a plated layer, comprising an upper surface, comprising electroplated or electroless plated copper or a copper alloy on the metal layer filling the opening; and

a layer of magnesium oxide, formed;

(a) directly on the upper surface of and encapsulating the plated layer; and

(b) directly on the entire surface of the metal layer lining the opening which is between the metal layer and the dielectric layer.

2. The semiconductor device according to claim 1, wherein the metal layer comprises an alloy containing about 0.1 to about 90 atomic percent Mg.