Apparatus and method for determining commutation time of sensorless brushless direct current (BLDC) motor

• US 6,249,096 B1
• Filed: 11/04/1999
• Issued: 06/19/2001
• Est. Priority Date: 11/13/1998
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Inventors: Shin, Hyun-Ick
• Primary Examiner(s): Nappi, Robert E.
• Assistant Examiner(s): Leykin, Rita
• Application Number:
  US09/434,038
• Time in Patent Office: 593 Days
• Field of Search: 318/254, 318/138, 318/439
• US Class Current: 318/400.06
• CPC Class Codes: H02P 6/14 Electronic commutators
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

Disclosed is an apparatus and a method for determining a commutation time of a three phase brushless direct current (BLDC) motor. The apparatus comprises a commutation controlling pulse generation unit receiving a phase voltage of each phase and generating a commutation controlling pulse to determine a commutation time of each phase of the motor; a first counter receiving a first commutation controlling pulse output from the commutation controlling pulse generator and counting the period of commutation controlling pulses; a memory storing one half of the counted values of the period of the first commutation controlling pulses counted by the first counter; a first comparator comparing a counting value of a period of a commutation controlling pulse provided after the first commutation controlling pulse counted by the first counter with one half of the counted values of the first commutation controlling pulses stored in the memory; and an output controller receiving the comparison result of the first comparator and outputting a switching signal to control commutation of each phase of the motor. The method comprises the steps of receiving variations of the BEMF of each phase of the motor and generating commutation controlling pulses for determining a commutation time; counting the period of the commutation controlling pulses; storing one half of counted values of the counted period of the commutation controlling pulses in a memory; counting a period of the commutation controlling pulses provided after the counted commutation controlling pulses; comparing counted number of the commutation controlling pulses input during the counting operation with the value stored in the memory; and generating a switching pulse to perform commutation of each phase of the motor when the comparison results are identical.

Claims

1. In a sensorless three phase brushless direct current (BLDC) motor which determines a commutation time by detecting a back electromotive force (BEMF) generated in a coil of each phase of the motor, an apparatus for determining a commutation time of a three phase BLDC motor, comprising:

a commutation controlling pulse generation unit receiving a phase voltage of each phase and generating a commutation controlling pulse to determine a commutation time of each phase of the motor;

a first counter receiving a first commutation controlling pulse output from the commutation controlling pulse generator and counting a period of commutation controlling pulses;

a memory storing one half of the counted values of the period of the first commutation controlling pulses-counted by the first counter;

a first comparator comparing a counted value of a period of commutation controlling pulse provided after the first commutation controlling pulse counted by the first counter with one half of the counted values of the period of first commutation controlling pulses stored in the memory; and

an output controller receiving the comparison result of the first comparator and outputting a switching signal to control commutation of each phase of the motor.

2. The apparatus of claim 1, wherein the apparatus further comprises:

a second counter receiving the switching signal and counting the period of switching signals; and

a second comparator receiving and comparing one half of the counted value stored in the memory and the counted numbers of the second counter and outputting the comparison result to the output controller.

3. The apparatus of claim 2, wherein the output controller receives the output signals of the second comparator and outputs a switching noise removing signal to remove switching noises.

4. The apparatus of claim 3, wherein the commutation controlling pulse generation unit comprises:

a reference pulse generator receiving phase voltages of each phase of the motor and voltage of a neutral point, and outputting a reference pulse having a uniform period; and

a commutation controlling pulse generator receiving the reference pulse of the reference pulse generator, switching signal, and switching noise removing signal of the output controller, and outputting a commutation controlling pulse generating as gate pulse type output each time a logic value of the reference pulse is changed.

5. The apparatus of claim 4, wherein the reference pulse generator comprises:

third, fourth, and fifth comparators having positive terminals to which phase voltages of the three phases are input, and having negative terminals to which voltage of the neutral point is supplied;

a first logic NAND gate performing a logic NAND operation on the outputs of the third and fourth comparators;

a second logic NAND gate performing a logic NAND operation on the outputs of the fourth and fifth comparators;

a third logic NAND gate performing a logic NAND operation on the outputs of the third and fifth comparators;

a first logic AND gate performing a logic AND operation on the outputs of the first, second, and third logic NAND gates and outputting a reference pulse, a period of the reference pulse being twice the period of commutation of the motor.

6. The apparatus of claim 4, wherein the commutation controlling pulse generator comprises:

a latch receiving the switching noise removing signal and the switching noise of the output controllers and outputting low logic values from the input time of the switching signal to the input time of the switching noise removing signal so that input of clock signals is prevented;

a second logic AND gate performing a logic AND operation on the output logic value of the latch and a clock signal and outputting a result;

a first flip-flop receiving the output of the second logic AND gate through a clock signal input terminal and the reference pulse of the reference pulse generator through an input terminal, and outputting the reference pulse to an output terminal according to the clock signals and the outputs of the second logic AND gate;

a second flip-flop receiving the output of the first flip-flop through an input terminal and the clock signals through another input terminal and outputting an output to the output terminal of the first flip-flop according to the clock signals;

a third flip-flop receiving the output of the second flip-flop and the clock signals, and outputting the output of the second flip-flop to an output terminal;

a first inverter coupled to the output terminal of the second flip-flop;

a fourth logic NAND gate receiving an output of the first inverter and an output of the third flip-flop and performing a logic NAND operation on the received signals;

a second inverter coupled to the output terminal of the third flip-flop;

a fifth logic NAND gate performing a logic NAND operation on the output values of the second flip-flop and the second inverter; and

a sixth logic NAND gate performing a logic NAND operation on the output values of the fourth and fifth logic NAND gates,

and wherein the apparatus generates a gate type pulse output each time the logic value of the reference pulse is changed.

7. The apparatus of claim 1, wherein the first counter counts a period of the first commutation controlling pulse by binary values using the clock pulses.

8. The apparatus of claim 1, wherein the memory stores the binary values counted by the first counter except for the least significant bit (LSB).

9. The apparatus of claim 1, wherein the first comparator compares the counted numbers of the commutation controlling pulses provided after the first commutation controlling pulse and one half of the counted number of the first commutation controlling pulse stored in the memory, and when the compared values are identical, outputs a first logic value.

10. The apparatus of claim 1, wherein the output controller comprises:

an enable signal generator receiving the commutation controlling pulse and, when the period of the commutation controlling pulse is constant, outputting an enable signal to output the switching signal;

an excess counting preventer receiving counted binary values of the first counter and, when the counting binary values exceeds the capacity of the counter, stopping the operation of the first counter;

a pre-switching noise removing signal generator receiving the commutation controlling pulse, switching signal, and the counted binary value of the second comparator, and generating a pre-switching noise removing signal for generating switching noise removing signals to remove switching noise;

a switching noise removing signal generator receiving the pre-switching noise removing signal from the pre-switching noise removing signal generator and counted binary value of the first counter, and removing switching noise generated by switching operations;

a pre-switching signal generator receiving an output of the first comparator and outputting an pre-switching signal for generating switching signals; and

a switching signal generator receiving the output binary values of the first counter and the pre-switching signal, and outputting a switching signal for performing commutation of each phase of the motor.

11. The apparatus of claim 10, wherein the enable signal generator comprises:

a fourth flip-flop receiving the commutation controlling pulse through a clock signal input terminal, and a logic NOT value of a previous signal from an output terminal through an input terminal, and outputting an input signal to the output terminal according to the commutation controlling pulse;

a third inverter coupled to the output terminal of the fourth flip-flop; and

a fifth flip-flop receiving an output signal of the third inverter through a clock signal input terminal and a high logic value through an input terminal, and outputting a high logic value to an output terminal according to the output signal of the third inverter.

12. The apparatus of claim 10, wherein the excess counting preventer comprises:

a seventh logic NAND gate performing logic NAND operation on inverted values of predetermined less significant bits of the counted binary values of the first counter and logic values of remaining bits;

a sixth flip-flop receiving an output value of the seventh logic NAND gate through a clock signal input terminal, and a logic high value through an input terminal, and outputting a logic high value according to an output value of an output logic value of the seventh logic NAND gate;

a fourth inverter coupled to an output terminal of the sixth flip-flop; and

a second logic AND gate performing a logic AND operation on the output value of the fourth inverter and the clock signal, and outputting the result to the clock signal input terminal of the first counter,

and wherein the clock signal is prevented from being input to the first counter when the counted binary values of the counter reaches a predetermined value.

13. The apparatus of claim 10, wherein the pre-switching noise removing signal generator comprises:

a seventh flip-flop receiving the clock signal through a clock signal input terminal, and an output value of the second comparator through an input terminal, and outputting an input value to an output terminal according to the clock signal;

a fifth inverter coupled to the seventh flip-flop; and

an eighth logic NAND gate receiving an output value of the fifth inverter and the enable signal and performing a logic NAND operation on received signals and outputting a signal.

14. The apparatus of claim 10, wherein the switching noise removing signal generator comprises:

a ninth logic NAND gate receiving the output counting binary value of the first counter and performing a logic NAND operation on inverted logic values of the predetermined less significant bits of the first counter and logic values of remaining bits;

an eighth flipflop receiving the pre-switching noise removing signal of the pre-switching noise removing signal generator through a clock signal input terminal, and a logic high value through an input terminal, and outputting a logic high value to an output terminal according to the pre-switching noise removing signal; and

a first logic OR gate performing a logic OR operation on the output value of the eighth flip-flop and the pre-switching noise removing signal of the pre-switching noise removing signal generator, and outputting a result.

15. The apparatus of claim 10, wherein the pre-switching signal generator comprises:

a ninth flip-flop receiving the output value of the first comparator through an input terminal and the clock signals through a clock signal input terminal, and outputting output values of the first comparator to an output terminal according to the clock signals;

a seventh inverter coupled to an output terminal of the ninth flip-flop; and

a tenth logic NAND gate performing a logic NAND operation on the output value of the seventh inverter and the output enable signal of the enable signal generator and outputting the result.

16. The apparatus of claim 10, wherein the switching signal generator comprises:

an eleventh logic NAND gate receiving an output counted binary value of the first counter and performing a logic NAND operation on inverted logic values of predetermined less significant bits of the first counter and logic values of remaining bits;

a tenth flip-flop receiving the pre-switching signal of the pre-switching signal generator through a clock signal input terminal, and a logic high value through an input terminal, and an output logic value of the eleventh logic NAND gate through a reset signal input terminal, and outputting a signal to an output terminal according to the pre-switching signal; and

a second OR gate performing a logic OR operation on an output logic value of the output of the tenth flip-flop and the pre-switching signal of the pre-switching signal generator, and outputting a result.

17. In a sensorless three phase brushless direct current (BLDC) motor which determines a commutation time by detecting a back electromotive force (BEMF) generated in a coil of each phase of the motor, a method for determining a commutation time of a three phase BLDC motor, comprising the steps of:

receiving variations of the BEMF of each phase of the motor and generating commutation controlling pulses for determining a commutation time;

counting a duration of a period commutation controlling pulses;

storing one half of counted value of the counted period of commutation controlling pulses in a memory;

counting a period of the commutation controlling pulses provided after the counted period commutation controlling pulses;

comparing a counted number of the commutation controlling pulses input during the counting operation with the value stored in the memory; and

generating a switching pulse to perform commutation of each phase of the motor when the comparison results are identical.

18. The method of claim 17, wherein the method further comprises the steps of:

counting the period of commutation controlling pulses after the switching pulse is generated;

generating a switching noise removing signal in order to prevent a change of a logic value of the commutation controlling pulse after the generation of the switching pulse;

comparing whether or not the counted number of the switching pulse is identical with one half of the value stored in the memory; and

stopping the changes of the logic values of the commutation controlling pulse when the comparison results are identical so that the generation of a signal to remove noises at time of switching operation is stopped.