Semiconductor integrated circuit, semiconductor device, and electronic equipment comprising the same
First Claim
1. A semiconductor integrated circuit comprising:
- at least one first semiconductor circuit operating on the basis of at least one first clock signal;
at least one second semiconductor circuit that assists said first semiconductor circuit, operating on the basis of a request from said first semiconductor circuit and at least one second clock signal independent of said first clock signal; and
a halt device that causes said second clock signal to halt, said halt device comprising;
a control signal generation device that generates at least one clock control signal for controlling halting and non-halting of said second clock signal;
an operation control device that controls halting of operation of said second clock signal, based on said clock control signal;
a setting device that causes a halt period to be set for said second clock signal, based on a request from said first semiconductor circuit; and
a counter device that counts an operating period of said second clock signal and outputs the counted counter value to said operation control device;
said operation control device outputting said clock control signal of said control signal generation device, to halt said second clock signal, when said counter value has reached said halt period.
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Accused Products
Abstract
The semiconductor integrated circuit of this invention comprises at least one first semiconductor circuit (10) that is driven on the basis of on at least one first clock signal (20). In addition, there is at least one second semiconductor circuit (50) assisting the first semiconductor circuit (10), which operates on the basis of at least one second clock signal (92) independent of the first clock signal (20) and a request from the first semiconductor circuit (10). The second semiconductor circuit (50) comprises a halt means (51) that causes the second clock signal (92) to halt if necessary. This makes it possible to halt the second clock signal (92), thus halting the operation of the second semiconductor circuit (50).
73 Citations
22 Claims
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1. A semiconductor integrated circuit comprising:
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at least one first semiconductor circuit operating on the basis of at least one first clock signal;
at least one second semiconductor circuit that assists said first semiconductor circuit, operating on the basis of a request from said first semiconductor circuit and at least one second clock signal independent of said first clock signal; and
a halt device that causes said second clock signal to halt, said halt device comprising;
a control signal generation device that generates at least one clock control signal for controlling halting and non-halting of said second clock signal;
an operation control device that controls halting of operation of said second clock signal, based on said clock control signal;
a setting device that causes a halt period to be set for said second clock signal, based on a request from said first semiconductor circuit; and
a counter device that counts an operating period of said second clock signal and outputs the counted counter value to said operation control device;
said operation control device outputting said clock control signal of said control signal generation device, to halt said second clock signal, when said counter value has reached said halt period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
wherein each of said operation control device, said counter device, and said control signal generation device is provided with a transistor of a first conductivity type and a transistor of a second conductivity type having a conductivity opposite to said first conductivity type; - and
wherein said transistor of the first conductivity type of said counter device is electrically disconnected from said transistors of the first conductivity type of said operation control device and said control signal generation device, and also said transistor of the second conductivity type of said counter device is electrically connected to said transistors of the second conductivity type of said operation control device and said control signal generation device.
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3. The semiconductor integrated circuit as defined in claim 1, wherein said setting device comprises:
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a storage device that stores said halt period for said second clock signal; and
a data write device that writes said halt period to at least said storage device, based on a request from said first semiconductor circuit.
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4. The semiconductor integrated circuit as defined in claim 1,
wherein said second semiconductor circuit includes a power supply circuit that supplies a potential to said second semiconductor circuit and a control circuit that controls said power supply circuit; - and
wherein said control signal generation device outputs a control signal for controlling said control circuit, to said control circuit.
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5. The semiconductor integrated circuit as defined in claim 4,
wherein each of said counter device, said operation control device and said control signal generation device in said second semiconductor circuit operates by using said power supply circuit as a power source. -
6. The semiconductor integrated circuit as defined in claim 5,
wherein said second semiconductor circuit is a time measurement circuit. -
7. The semiconductor integrated circuit as defined in claim 1,
wherein said second semiconductor circuit further comprises an input-output device that inputs and outputs data between a data maintenance device and said operation control device and said control signal generation device. -
8. A semiconductor device comprising:
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the semiconductor integrated circuit defined in claim 1;
a first power supply circuit that shapes a voltage to be supplied to said first semiconductor circuit of said semiconductor integrated circuit; and
a second power supply circuit that shapes a voltage to be supplied to said second semiconductor circuit of said semiconductor integrated circuit;
wherein all said circuits are formed on the same substrate.
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9. A semiconductor device comprising:
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the semiconductor integrated circuit defined in claim 1;
a first oscillation circuit that forms said first clock signal;
a second oscillation circuit that forms said second clock signal;
a dedicated power supply for a substrate on which said semiconductor integrated circuit and said first and second oscillation circuits are formed, that supplies power to each circuit on said substrate.
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10. Electronic equipment comprising the semiconductor device defined in claim 8.
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11. Electronic equipment comprising the semiconductor device defined in claim 9.
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12. The semiconductor integrated circuit as defined in claim 1, the halt device being part of said second semiconductor circuit.
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13. A semiconductor integrated circuit comprising:
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at least one first semiconductor circuit operating on the basis of at least one first clock signal;
at least one second semiconductor circuit that assists said first semiconductor circuit, operating on the basis of a request from said first semiconductor circuit and at least one second clock signal independent of said first clock signal;
a half device that causes said second clock signal to halt; and
an input-output device that transfers data between said second semiconductor circuit and said first semiconductor circuit. - View Dependent Claims (14, 15, 16, 17)
the semiconductor integrated circuit defined in claim 13;
a first power supply circuit that shapes a voltage to be supplied to said first semiconductor circuit of said semiconductor integrated circuit; and
a second power supply circuit that shapes a voltage to be supplied to said second semiconductor circuit of said semiconductor integrated circuit;
wherein all said circuits are formed on the same substrate.
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15. A semiconductor device comprising:
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the semiconductor integrated circuit defined in claim 13;
a first oscillation circuit that forms said first clock signal;
a second oscillation circuit that forms said second clock signal; and
a dedicated power supply for a substrate on which said semiconductor integrated circuit and said first and second oscillation circuits are formed, that supplies power to each circuit on said substrate.
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16. Electronic equipment comprising the semiconductor device defined in claim 14.
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17. Electronic equipment comprising the semiconductor device defined in claim 15.
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18. A semiconductor integrated circuit comprising:
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at least one first semiconductor circuit operating on the basis of at least one first clock signal;
at least one second semiconductor circuit that assists said first semiconductor circuit, operating on the basis of a request from said first semiconductor circuit and at least one second clock signal independent of said first clock signal; and
a halt device that causes said second clock signal to halt, wherein said first semiconductor circuit comprises;
a main power supply circuit that supplies a potential to said first semiconductor circuit; and
a main power supply control circuit that controls said main power supply circuit by outputting a power supply halt signal based on said first clock signal, for halting said main power supply circuit. - View Dependent Claims (19, 20, 21, 22)
the semiconductor integrated circuit defined in claim 18;
a first power supply circuit that shapes a voltage to be supplied to said first semiconductor circuit of said semi conductor integrated circuit; and
a second power supply circuit that shapes a voltage to be supplied to said second semiconductor circuit of said semiconductor integrated circuit;
wherein all said circuits are formed on the same substrate.
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20. A semiconductor device comprising:
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the semiconductor integrated circuit defined in claim 18;
a first oscillation circuit that forms said first clock signal;
a second oscillation circuit that forms said second clock signal; and
a dedicated power supply for a substrate on which said semiconductor integrated circuit and said first and second oscillation circuits are formed, that supplies power to each circuit on said substrate.
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21. Electronic equipment comprising the semiconductor device defined in claim 19.
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22. Electronic equipment comprising the semiconductor device defined in claim 20.
Specification