Transistor output circuit

• US 6,249,169 B1
• Filed: 12/29/1998
• Issued: 06/19/2001
• Est. Priority Date: 06/01/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Fujitsu Limited
• Inventors: Okada, Koji
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US09/221,989
• Time in Patent Office: 903 Days
• Field of Search: 327/437, 327/442, 327/108, 327/374, 327/376, 327/377, 327/387, 327/333, 327/281
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A transistor output circuit generates an output signal having a voltage greater than a breakdown voltage of the transistors used to construct the output circuit. The output circuit includes an NMOS transistor and a PMOS transistor that are connected in series and have their gates connected to each other. A potential control circuit is also connected to the gates and the sources of the NMOS and PMOS transistors. The potential control circuit receives power from a high potential power supply and a low potential power supply. The potential control circuit applies a reference voltage, which has a voltage value between the voltages generated by the high and low potential power supplies, to the gates of the transistors. Then, in response to an input signal, the potential control circuit controls the voltages applied to the sources of the transistors. The output circuit may be connected to a level converter circuit, an op amp circuit, and other logic circuits.

Claims

1. An output circuit comprising:

a PMOS transistor and a NMOS transistor connected in series and a potential control circuit connected to the gate and source of the PMOS and the NMOS transistor, for receiving power from a high potential power supply and a low potential power supply, and controlling the voltage applied to the gate and the source of the PMOS transistor and the NMOS transistor in response to an input signal having one of a first level and a second level,

wherein the potential control circuit applies a reference voltage to the gates of the PMOS transistor and the NMOS transistor, the reference voltage being between the high potential power supply level and the low potential power supply voltage level,

wherein the potential control circuit applies the high potential power supply voltage to the source of the PMOS transistor in response to said input signal with the first level and applies a first voltage to the source of the NMOS transistor to make the NMOS transistor nonconductive, so that an output signal with the high potential power supply voltage is output from a node between the PMOS transistor and the NMOS transistor, and

wherein the potential control circuit applies the low potential power supply voltage to the source of the NMOS transistor in response to said input signal having the second level and applies a second voltage to the source of the PMOS transistor to make the PMOS transistor nonconductive, so that an output signal having the low potential power supply voltage is output from the node between the PMOS transistor and the NMOS transistor, and wherein an amplitude of the output signal exceeds a breakdown voltage of the PMOS transistor and the NMOS transistor.

2. The output circuit according to claim 1, wherein the reference voltage is an intermediate voltage between the high potential power supply voltage and the low potential power supply voltage.

3. An output circuit, comprising:

a PMOS transistor and an NMOS transistor connected in series;

a first source follower circuit connected between the source of the PMOS transistor and a high potential power supply, for selectively applying a high potential power supply voltage to the source of the PMOS transistor in response to a first input signal having a voltage that changes between the high potential power supply voltage and a reference voltage, the reference voltage being between the high potential power supply voltage and a low potential power supply voltage;

a second source follower circuit connected between the source of the NMOS transistor and a low potential power supply, for selectively applying the low potential power supply voltage to the source of the NMOS transistor in response to a second input signal having a voltage that changes between the reference voltage and low potential power supply voltage; and

an output terminal located at a node between the PMOS transistor and the NMOS transistor for outputting an output signal having one of the high potential power supply voltage and the low potential power supply voltage.

4. The output circuit according to claim 3, further comprising a reference voltage generation circuit connected to the gates of the PMOS transistor and NMOS transistor, for generating the reference voltage and applying the reference voltage to the gates of the PMOS transistor and NMOS transistor.

5. The output circuit according to claim 3, wherein the reference voltage is an intermediate voltage between the high potential power supply voltage and the low potential power supply voltage.

6. The output circuit according to claim 3,

wherein supply of the first and second input signals is timed such that the source voltage of the NMOS transistor changes earlier than the source voltage of the PMOS transistor when the output signal is rising from the low potential power supply voltage to the high potential power supply voltage and the source voltage of the NMOS transistor changes later than the source voltage of the PMOS transistor when the output signal is falling from the high potential power supply voltage to the low potential power supply voltage.

7. An output circuit, comprising;

a PMOS transistor and a NMOS transistor connected in series;

a first inverter circuit connected to the source of the PMOS transistor, for receiving power from a high potential power supply and a reference voltage between the high potential power supply voltage and a low potential power supply voltage, the first inverter receiving a first input signal having a voltage that changes between the high potential power supply voltage and the reference voltage and applying one of the high potential power supply voltage and reference voltage to the source of the PMOS transistor;

a second inverter circuit connected to the source of the NMOS transistor for receiving power from the reference voltage and a low potential power supply, the second inverter circuit receiving a second input signal having a voltage that changes between the reference voltage and the low power supply voltage and applying one of the reference voltage and the low potential power supply voltage to the source of the NMOS transistor; and

an output terminal located at a node between the PMOS transistor and the NMOS transistor for outputting an output signal having one of the high potential power supply voltage and the low potential power supply voltage.

8. The output circuit according to claim 7, further comprising a reference voltage generation circuit connected to the gates of the PMOS transistor and the NMOS transistor, for generating the reference voltage and applying the reference voltage to the gates of the PMOS transistor and the NMOS transistor.

9. The output circuit according to claim 7, wherein the reference voltage is intermediate between the high potential power supply voltage and the low potential power supply voltage.

10. The output circuit according to claim 7,

wherein supply of the first and second input signals is timed such that the source voltage of the NMOS transistor changes earlier than the source voltage of the PMOS transistor when the output signal is rising from the low potential power supply voltage to the high potential power supply voltage and the source voltage of the NMOS transistor changes later than the source voltage of the PMOS transistor when the output signal is falling from the high potential power supply voltage to the low potential power supply voltage.

11. A level converter circuit, comprising:

an input signal converter for receiving power from a high potential power supply and a low potential power supply and converting an external input signal to first and second input signals, the first input signal having a voltage that changes between the high potential power supply voltage and a reference voltage, the reference voltage being between the high potential power supply voltage and the low potential power supply voltage, the second input signal having a voltage that changes between the reference voltage and the low potential power supply voltage; and

an output circuit connected to the input signal converter, for receiving the first and second input signals and outputting an output signal having one of the high potential power supply voltage and the low potential power supply voltage.

12. The level converter circuit according to claim 11,

wherein the output circuit further comprises:

a PMOS transistor and an NMOS transistor connected in series;

a first source follower circuit connected between the source of the PMOS transistor and the high potential power supply, for selectively applying the high potential power supply voltage to the source of the PMOS transistor in response to the first input signal;

a second source follower circuit connected between the source of the NMOS transistor and the low potential power supply, for selectively applying the low potential power supply voltage to the source of the NMOS transistor in response to the second input signal; and

an output terminal located at a node between the PMOS transistor and NMOS transistor that outputs the output signal.

13. The level converter according to claim 11,

wherein the output circuit further comprises:

a PMOS transistor and an NMOS transistor connected in series;

a first inverter circuit connected to the source of the PMOS transistor, for receiving power from the high potential power supply and the reference voltage, the first inverter circuit receiving the first input signal and applying one of the high potential power supply voltage and the reference voltage to the source of the PMOS transistor;

a second inverter circuit connected to the source of the NMOS transistor, for receiving power from the reference voltage and the low potential power supply, the second inverter circuit receiving the second input signal and applying one of the reference voltage and the low potential power supply voltage to the source of the NMOS transistor; and

an output terminal located at a node between the PMOS transistor and the NMOS transistor for outputting an output signal.

14. The level converter circuit according to claim 11,

wherein the input signal converter comprises:

a first current mirror circuit and a first resistor connected in series between the high potential power supply and the reference voltage;

a first switching circuit for selectively activating the first current mirror circuit in response to the external input signal, the first input signal being supplied to the output circuit from a node between the first current mirror circuit and the first resistor;

a second current mirror circuit and a second resistor connected in series between the reference voltage and the low potential power supply; and

a second switching circuit for selectively activating the second current mirror circuit in response the external input signal, the second input signal being supplied to the output circuit from a node between the second current mirror circuit and the second resistor.

15. The level converter circuit according to claim 11,

wherein the input signal converter comprises:

first and second current mirror circuits connected between the high potential power supply and the reference voltage;

a first switching circuit for selectively activating the first current mirror circuit in response to the external input signal;

a second switching circuit for activating the second current mirror circuit complementarily with the first current mirror circuit based on the external input signal, the first input signal being supplied to the output circuit from a node between the first and second current mirror circuits;

third and fourth current mirror circuits connected between the reference voltage and the low potential power supply;

a third switching circuit for selectively activating the third current mirror circuit in response to the external input signal; and

a fourth switching circuit for activating the fourth current mirror circuit complementarily with the third current mirror circuit in response to the external input signal, the second input signal being supplied to the output circuit from a node between the third and fourth current mirrors circuits.

16. The level converter circuit according to claim 11, wherein the external input signal changes between the reference voltage and low potential power supply voltage, the input signal converter comprising:

first and second current mirror circuits connected between the high potential power supply and the reference voltage;

a first switching circuit for selectively activating the first current mirror in response to the external input signal;

a second switching circuit for activating the second current mirror circuit complementarily with the first current mirror circuit in response to the external input signal, the first input signal being supplied to the output circuit from a node between the first and second mirror circuits; and

an inverter for receiving the external input signal and supplying the second input signal to the output circuit.

17. The level converter circuit according to claim 11, wherein the input signal converter comprises:

a one-shot circuit for converting the external input signal to first and second one-shot pulse signals;

a first switching circuit and a first current mirror circuit connected in series between the high potential power supply and the low potential power supply, the first switching circuit selectively activating the first current mirror circuit in response to the first one-shot pulse signal;

a second switching circuit and a second current mirror circuit connected in series between the high potential power supply and the low potential power supply, the second switching circuit activating the second current mirror circuit complementarily with the first current mirror circuit in response to the second one-shot pulse signal;

a first latch circuit connected between the first and second current mirror circuits, for latching the first input signal while the external input signal is changing, the first input signal being supplied to the output circuit from a node between the second current mirror circuit and the first latch circuit;

a third switching circuit and a third current mirror circuit connected in series between the reference voltage and low potential power supply, the third switching circuit selectively activating the third current mirror circuit in response to the first one-shot pulse signal;

a fourth switching circuit and a fourth current mirror circuit connected between the reference voltage and the low potential power supply, the fourth switching circuit activating the fourth current mirror circuit complementarily with the third current mirror circuit in response to the second one-shot pulse signal; and

a second latch circuit connected between the third and fourth current mirror circuits for latching the second input signal while the external input signal changes, the second input signal being supplied to the output circuit from a node between the fourth current mirror circuit and the second latch circuit.

18. A logic circuit, comprising:

first and second power supplies for shifting voltages of first and second input signals, thereby generating first and second shifted input signals;

an output circuit connected to the first and second power supplies, for receiving the first and second input signals and the first and second shifted input signals and outputting a predetermined logical signal, the output circuit including;

a PMOS transistor and a NMOS transistor connected in series;

a first NAND circuit connected to the source of the PMOS transistor and receiving power from the high potential power supply and a reference voltage, the reference voltage being between the high potential power supply voltage and the low potential voltage power supply, the first NAND circuit receiving the first and second shifted input signals and applying one of the high potential power supply voltage and the reference voltage to the source of the PMOS transistor;

a second NAND circuit connected to the source of the NMOS transistor and receiving power from the reference voltage and the low potential power supply, the second NAND circuit receiving the first and second input signals and applying one of the reference voltage and the low potential power supply voltage to the source of the NMOS transistor; and

an output terminal located at a node between the PMOS transistor and NMOS transistor for outputting a logical signal.

19. An operational amplifier, comprising:

an input circuit for receiving power from a high potential power supply and a low potential power supply and generating first and second voltage signals by comparing first and second input signals with each other, the first signal having one of the high potential power supply voltage and a reference voltage, the reference voltage being between the high potential power supply voltage and the low potential power supply voltage, the second voltage signal having one of the reference voltage and the low potential power supply voltage; and

an output circuit connected to the input circuit for receiving the first and second voltage signals and outputting an output signal having one of the high potential power supply voltage and the low potential power supply voltage.

20. The operational amplifier according to claim 19, wherein the output circuit comprises:

a PMOS transistor and an NMOS transistor connected in series;

a first inverter circuit connected to the source of the PMOS transistor and receiving power from the high potential power supply and the reference voltage, the first inverter circuit receiving the first voltage signal and applying one of the high potential power supply voltage and the reference voltage to the source of the PMOS transistor;

a second inverter circuit connected to the source of the NMOS transistor and receiving power from the reference voltage and the low potential power supply, the second inverter circuit receiving the second voltage signal and applying one of the reference voltage and the low potential power supply voltage to the source of the NMOS transistor; and

an output terminal located at a node between the PMOS transistor and the NMOS transistor for outputting an output signal.

21. The operational amplifier circuit according to claim 19, wherein the input circuit comprises:

a constant current source connected between the high potential power supply and the low potential power supply;

first and second transistors and a current mirror circuit connected in series between the constant current source and the high potential power supply, the first transistor being responsive to the first input signal and the second transistor being responsive to the reference voltage; and

first and second resistors and a third transistor connected in series between the current mirror circuit and the constant current source, wherein the first voltage signal is supplied to the output circuit from a node between the current mirror circuit and the first resistor, and the second voltage signal is supplied to the output circuit from a node between the third transistor and the second resistor.