Low power seismic device interface and system for capturing seismic signals

• US 6,249,236 B1
• Filed: 04/03/1998
• Issued: 06/19/2001
• Est. Priority Date: 04/03/1998
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Thomsen, Axel, Lee, Wai Laing, Kasha, Dan
• Primary Examiner(s): Wamsley, Patrick
• Application Number:
  US09/054,544
• Time in Patent Office: 1,173 Days
• Field of Search: 341/143, 341/172, 341/144, 341/145, 341/156, 341/122, 341/123, 367/36, 367/65, 375/242, 330/9
• US Class Current: 341/143
• CPC Class Codes: G01V 1/245 Amplitude control for seismic recording control of amplification in general H03G
• CPC Class Codes: H03M 3/32 with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/448 by removing part of the zeroes, e.g. using local feedback loops
• CPC Class Codes: H03M 3/452 with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input

Abstract

A front end for capturing seismic signals uses a voltage doubling circuit and an analog to digital converter (ADC) having different power levels available during respective operational phases. Power available the ADC is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. Increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. A large step size is selected for the ADC to reduce power consumption for a delta sigma modulator used in the ADC and feedback coefficients are optimized for low power by running at a higher oversampling rate than required by signal to quantization noise requirements.

Claims