Method for designing a tiled memory

• US 6,249,475 B1
• Filed: 04/05/1999
• Issued: 06/19/2001
• Est. Priority Date: 04/05/1999
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Madrone Solutions, Inc.
• Inventors: Myers, Jeffrey Van, Atwell, William Daune, Longwell, Michael L.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US09/286,186
• Time in Patent Office: 806 Days
• Field of Search: 365/189.08, 365/189.09, 365/200, 365/226, 365/230.03, 365/63
• US Class Current: 365/230.03
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c′, 32c″).

Claims

1. A method for designing a tiled memory, comprising the steps of:

designing a memory tile, comprising the steps of;

designing a memory cell having predetermined charge requirements;

arranging a plurality of said memory cells in a cell array;

determining the total charge requirements of said memory cells comprising said cell array;

designing a charge source to supply said total charge requirements; and

integrating said charge source and said cell array to form said memory tile;

arranging a plurality of said memory tiles to form a tile array;

designing an interface for selectively coupling the memory tiles to external logic; and

integrating said interface and said tile array to form said tiled memory.

2. The method of claim 1 wherein each charge source is designed to include a plurality of atomic charge pumps.

3. The method of claim 2 wherein the plurality of atomic charge pumps are designed to operate sequentially.

4. The method of claim 3 wherein the number of atomic charge pumps operating sequentially is designed to be selectable.

5. The method of claim 4 wherein each memory tile is designed to include a voltage level detector coupled to the charge source, the voltage level detector being designed to detect incorrect operation of said charge source.

6. The method of claim 5 wherein the voltage level detector is designed to provide an output signal in response to detecting incorrect operation of said charge source.

7. The method of claim 6 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.

8. The method of claim 7 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

9. The method of claim 8 wherein the fault logic is designed to include error correction logic.

10. The method of claim 9 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

11. The method of claim 10 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

12. The method of claim 11 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

13. The method of claim 12 wherein the memory cells are arranged in an array of rows and columns.

14. The method of claim 13 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

15. The method of claim 14 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

16. The method of claim 13 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

17. The method of claim 5 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.

18. The method of claim 17 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

19. The method of claim 18 wherein the fault logic is designed to include error correction logic.

20. The method of claim 19 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

21. The method of claim 20 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

22. The method of claim 21 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

23. The method of claim 22 wherein the memory cells are arranged in an array of rows and columns.

24. The method of claim 23 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

25. The method of claim 24 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

26. The method of claim 23 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

27. The method of claim 4 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

28. The method of claim 27 wherein the fault logic is designed to include error correction logic.

29. The method of claim 28 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

30. The method of claim 29 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

31. The method of claim 30 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

32. The method of claim 31 wherein the memory cells are arranged in an array of rows and columns.

33. The method of claim 32 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

34. The method of claim 33 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

35. The method of claim 32 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

36. The method of claim 4 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

37. The method of claim 36 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

38. The method of claim 37 wherein the memory cells are arranged in an array of rows and columns.

39. The method of claim 38 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

40. The method of claim 39 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

41. The method of claim 38 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

42. The method of claim 1 wherein each memory tile is designed to include a voltage level detector coupled to the charge source, the voltage level detector being designed to detect incorrect operation of said charge source.

43. The method of claim 42 wherein the voltage level detector is designed to provide an output signal in response to detecting incorrect operation of said charge source.

44. The method of claim 43 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.

45. The method of claim 44 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

46. The method of claim 45 wherein the fault logic is designed to include error correction logic.

47. The method of claim 46 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

48. The method of claim 47 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

49. The method of claim 48 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

50. The method of claim 49 wherein the memory cells are arranged in an array of rows and columns.

51. The method of claim 50 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

52. The method of claim 51 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

53. The method of claim 50 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

54. The method of claim 42 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.

55. The method of claim 54 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

56. The method of claim 55 wherein the fault logic is designed to include error correction logic.

57. The method of claim 56 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

58. The method of claim 57 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

59. The method of claim 58 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

60. The method of claim 59 wherein the memory cells are arranged in an array of rows and columns.

61. The method of claim 60 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

62. The method of claim 61 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

63. The method of claim 60 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

64. The method of claim 1 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

65. The method of claim 64 wherein the fault logic is designed to include error correction logic.

66. The method of claim 65 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

67. The method of claim 66 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

68. The method of claim 67 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

69. The method of claim 68 wherein the memory cells are arranged in an array of rows and columns.

70. The method of claim 69 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

71. The method of claim 70 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

72. The method of claim 69 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

73. The method of claim 1 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

74. The method of claim 73 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

75. The method of claim 74 wherein the memory cells are arranged in an array of rows and columns.

76. The method of claim 75 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

77. The method of claim 76 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

78. The method of claim 75 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

79. The method of claim 1 wherein the charge source is designed to include a plurality of atomic voltage references.

80. The method of claim 79 wherein the atomic voltage references are designed to operate simultaneously.

81. The method of claim 80 wherein the number of atomic voltage references operating simultaneously is designed to be selectable.

82. The method of claim 81 wherein each memory tile is designed to include a voltage level detector coupled to the charge source, the voltage level detector being designed to detect incorrect operation of said charge source.

83. The method of claim 82 wherein the voltage level detector is designed to provide an output signal in response to detecting incorrect operation of said charge source.

84. The method of claim 83 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.

85. The method of claim 84 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

86. The method of claim 85 wherein the fault logic is designed to include error correction logic.

87. The method of claim 86 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

88. The method of claim 87 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

89. The method of claim 88 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

90. The method of claim 89 wherein the memory cells are arranged in an array of rows and columns.

91. The method of claim 90 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

92. The method of claim 91 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

93. The method of claim 90 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

94. The method of claim 82 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.

95. The method of claim 94 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

96. The method of claim 95 wherein the fault logic is designed to include error correction logic.

97. The method of claim 96 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

98. The method of claim 97 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

99. The method of claim 98 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

100. The method of claim 99 wherein the memory cells are arranged in an array of rows and columns.

101. The method of claim 100 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

102. The method of claim 101 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

103. The method of claim 100 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

104. The method of claim 81 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

105. The method of claim 104 wherein the fault logic is designed to include error correction logic.

106. The method of claim 105 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

107. The method of claim 106 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

108. The method of claim 107 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

109. The method of claim 108 wherein the memory cells are arranged in an array of rows and columns.

110. The method of claim 109 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

111. The method of claim 110 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

112. The method of claim 109 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

113. The method of claim 81 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

114. The method of claim 113 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

115. The method of claim 114 wherein the memory cells are arranged in an array of rows and columns.

116. The method of claim 115 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

117. The method of claim 116 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

118. The method of claim 115 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

119. The method of claim 1 wherein said memory tile further comprises access control logic.

120. The method of claim 119 wherein the access control logic comprises address buffers and timing logic.

121. The method of claim 1 wherein said memory tile further comprises data buffers coupled to the interface and to each of the memory cells.

122. The method of claim 121 wherein said memory tile further comprises sense amplifiers coupled between each of the memory cells and a respective one of said data buffers.

123. A method for designing an integrated circuit having a tiled memory, comprising the steps of:

designing a memory tile, comprising the steps of;

designing a memory cell having predetermined charge requirements;

arranging a plurality of said memory cells in a cell array;

determining the total charge requirements of said memory cells comprising said cell array;

designing a charge source to supply said total charge requirements; and

integrating said charge source and said cell array to form said memory tile;

arranging a plurality of said memory tiles to form a tile array;

designing an interface for selectively coupling the memory tiles to external logic; and

integrating said interface and said tile array to form said tiled memory in said integrated circuit.

124. The method of claim 123 wherein each charge source is designed to include a plurality of atomic charge pumps.

125. The method of claim 124 wherein the plurality of atomic charge pumps are designed to operate sequentially.

126. The method of claim 125 wherein the number of atomic charge pumps operating sequentially is designed to be selectable.

127. The method of claim 126 wherein each memory tile is designed to include a voltage level detector coupled to the charge source, the voltage level detector being designed to detect incorrect operation of said charge source.

128. The method of claim 127 wherein the voltage level detector is designed to provide an output signal in response to detecting incorrect operation of said charge source.

129. The method of claim 128 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.

130. The method of claim 129 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

131. The method of claim 130 wherein the fault logic is designed to include error correction logic.

132. The method of claim 131 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

133. The method of claim 132 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

134. The method of claim 133 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

135. The method of claim 134 wherein the memory cells are arranged in an array of rows and columns.

136. The method of claim 135 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

137. The method of claim 136 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

138. The method of claim 135 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

139. The method of claim 127 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.

140. The method of claim 139 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

141. The method of claim 140 wherein the fault logic is designed to include error correction logic.

142. The method of claim 141 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

143. The method of claim 142 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

144. The method of claim 143 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

145. The method of claim 144 wherein the memory cells are arranged in an array of rows and columns.

146. The method of claim 145 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

147. The method of claim 146 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

148. The method of claim 145 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

149. The method of claim 126 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

150. The method of claim 149 wherein the fault logic is designed to include error correction logic.

151. The method of claim 150 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

152. The method of claim 151 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

153. The method of claim 152 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

154. The method of claim 153 wherein the memory cells are arranged in an array of rows and columns.

155. The method of claim 154 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

156. The method of claim 155 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

157. The method of claim 154 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

158. The method of claim 126 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

159. The method of claim 158 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

160. The method of claim 159 wherein the memory cells are arranged in an array of rows and columns.

161. The method of claim 160 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

162. The method of claim 161 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

163. The method of claim 160 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

164. The method of claim 123 wherein each memory tile is designed to include a voltage level detector coupled to the charge source, the voltage level detector being designed to detect incorrect operation of said charge source.

165. The method of claim 164 wherein the voltage level detector is designed to provide an output signal in response to detecting incorrect operation of said charge source.

166. The method of claim 165 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.

167. The method of claim 166 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

168. The method of claim 167 wherein the fault logic is designed to include error correction logic.

169. The method of claim 168 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

170. The method of claim 169 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

171. The method of claim 170 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

172. The method of claim 171 wherein the memory cells are arranged in an array of rows and columns.

173. The method of claim 172 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

174. The method of claim 173 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

175. The method of claim 172 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

176. The method of claim 164 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.

177. The method of claim 176 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

178. The method of claim 177 wherein the fault logic is designed to include error correction logic.

179. The method of claim 178 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

180. The method of claim 179 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

181. The method of claim 180 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

182. The method of claim 181 wherein the memory cells are arranged in an array of rows and columns.

183. The method of claim 182 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

184. The method of claim 183 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

185. The method of claim 182 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

186. The method of claim 123 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

187. The method of claim 186 wherein the fault logic is designed to include error correction logic.

188. The method of claim 187 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

189. The method of claim 188 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

190. The method of claim 189 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

191. The method of claim 190 wherein the memory cells are arranged in an array of rows and columns.

192. The method of claim 191 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

193. The method of claim 192 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

194. The method of claim 191 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

195. The method of claim 123 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

196. The method of claim 195 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

197. The method of claim 196 wherein the memory cells are arranged in an array of rows and columns.

198. The method of claim 197 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

199. The method of claim 198 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

200. The method of claim 197 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

201. The method of claim 123 wherein the charge source is designed to include a plurality of atomic voltage references.

202. The method of claim 201 wherein the atomic voltage references are designed to operate simultaneously.

203. The method of claim 202 wherein the number of atomic voltage references operating simultaneously is designed to be selectable.

204. The method of claim 203 wherein each memory tile is designed to include a voltage level detector coupled to the charge source, the voltage level detector being designed to detect incorrect operation of said charge source.

205. The method of claim 204 wherein the voltage level detector is designed to provide an output signal in response to detecting incorrect operation of said charge source.

206. The method of claim 205 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.

207. The method of claim 206 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

208. The method of claim 207 wherein the fault logic is designed to include error correction logic.

209. The method of claim 208 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

210. The method of claim 209 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

211. The method of claim 210 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

212. The method of claim 211 wherein the memory cells are arranged in an array of rows and columns.

213. The method of claim 212 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

214. The method of claim 213 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

215. The method of claim 212 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

216. The method of claim 204 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.

217. The method of claim 216 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

218. The method of claim 217 wherein the fault logic is designed to include error correction logic.

219. The method of claim 218 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

220. The method of claim 219 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

221. The method of claim 220 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

222. The method of claim 221 wherein the memory cells are arranged in an array of rows and columns.

223. The method of claim 222 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

224. The method of claim 223 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

225. The method of claim 222 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

226. The method of claim 203 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.

227. The method of claim 226 wherein the fault logic is designed to include error correction logic.

228. The method of claim 227 wherein the fault logic is designed to detect double bit errors and correct single bit errors.

229. The method of claim 228 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

230. The method of claim 229 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

231. The method of claim 230 wherein the memory cells are arranged in an array of rows and columns.

232. The method of claim 231 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

233. The method of claim 232 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

234. The method of claim 231 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

235. The method of claim 203 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.

236. The method of claim 235 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.

237. The method of claim 236 wherein the memory cells are arranged in an array of rows and columns.

238. The method of claim 237 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.

239. The method of claim 238 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

240. The method of claim 237 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.

241. The method of claim 123 wherein said memory tile further comprises access control logic.

242. The method of claim 241 wherein the access control logic comprises address buffers and timing logic.

243. The method of claim 123 wherein said memory tile further comprises data buffers coupled to the interface and to each of the memory cells.

244. The method of claim 243 wherein said memory tile further comprises sense amplifiers coupled between each of the memory cells and a respective one of said data buffers.

245. The method of claim 243 wherein the step of arranging the plurality of said memory tiles is further characterized as arranging said memory tiles so that adjacent charge sources are coupled together.