Fully synchronous pipelined ram

• US 6,249,480 B1
• Filed: 10/28/1999
• Issued: 06/19/2001
• Est. Priority Date: 04/19/1996
• Status: Expired due to Term

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Mick, John R.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, TUAN T
• Application Number:
  US09/429,849
• Time in Patent Office: 600 Days
• Field of Search: 365/233, 365/191
• US Class Current: 365/233.1
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Claims

1. A memory structure, comprising:

A pipeline structure for receiving at least one read address and data information to be written into a memory at the at least one read address, wherein each of the at least one read address is received during a first cycle and the data for each of the at least one read address is received during a second cycle that is separated from the first cycle by p cycles, where p is an integer greater than one; and

a write structure that receives a write address during a third cycle, the write structure outputting during a fourth cycle data at the write address, the data being read from the pipeline structure if the write address corresponds to one of the at least one read address.

2. The structure of claim 1, wherein the pipeline structure includes at least one address register and at least one data register, the at least one address register and the at least one data register each latching information at an input terminal on a rising clock-edge signal.

3. The structure of claim 1, wherein the pipeline structure is suspended in response to an input signal.

4. The structure of claim 3, wherein the input signal is a chip enable signal.

5. The structure of claim 3, wherein the input signal is a chip select signal.

6. A processing system, comprising:

a processor;

a memory system coupled to the processor, the memory system comprising;

a pipeline structure for receiving at least one read address and data information to be written into a memory at the at least one read address from the processor, wherein each of the at least one read address is received from the processor during a first cycle and the data for each of the at least one read address is received from the processor during a second cycle that is separated from the first cycle by p cycles, where p is an integer greater than one; and

a write structure that receives a write address from the processor in a third cycle, the write structure outputting to the processor in a fourth cycle data at the write address, the data being read from the pipeline structure if the write address corresponds to one of the at least one read address.

7. The system of claim 6, wherein the pipeline structure includes at least one address register and at least one data register, the at least one address register and the at least one data register each latching information at an input terminal on a rising clock-edge signal.

8. The system of claim 6, wherein p is 1.

9. The system of claim 6, wherein p is 2.

10. The system of claim 6, wherein p is greater than 2.

11. A processing system, comprising:

a processor;

an address pipeline coupled to the processor;

a data pipeline coupled to a data terminal, the data terminal coupled to the processor;

a memory; and

a control logic coupled between the address pipeline, the data pipeline, and the memory;

wherein, in a write operation the address pipeline receives a write address from the processor in a first clock cycle and data to be written into the memory at the write address from the processor in a second clock cycle, the second clock cycle being p clock cycles following the first clock cycle; and

wherein, in a read operation the address pipeline receives a read address from the processor in a third clock cycle and data is presented to the processor in a first clock cycle, the fourth clock cycle being p clock cycles following the first clock cycle, p being a positive integer.

12. The system of claim 11, wherein the address pipeline includes at least one address register which latches an address at an input terminal on a rising clock edge.

13. The system of claim 11, wherein the data pipeline includes at least one data register which latches data at an input terminal on a rising clock edge.

14. The system of claim 11, wherein p is 1.

15. The system of claim 11, wherein p is 2.

16. The system of claim 11, where p is greater than 2.