System for expanding PCI bus loading capacity

• US 6,249,834 B1
• Filed: 10/01/1997
• Issued: 06/19/2001
• Est. Priority Date: 05/13/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Agneta, Don, Amdahl, Carlton G., Smith, Dennis H., Henderson, Michael G.
• Primary Examiner(s): Dharia, Rupal
• Application Number:
  US08/942,404
• Time in Patent Office: 1,357 Days
• Field of Search: 395/309, 710/103, 710/128, 710/129, 710/126, 710/260, 713/400
• US Class Current: 710/313
• CPC Class Codes: G06F 1/20 Cooling means
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 21/305 by remotely controlling device operation
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 41/22 comprising specially adapted graphical user interfaces [GUI]
• CPC Class Codes: H04L 67/1001 for accessing one among a plurality of replicated servers
• CPC Class Codes: H05K 7/20836 Thermal management, e.g. server temperature control
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A system for expanding the loading capacity of a PCI bus in an information processing system having a multiple bus architecture. In one embodiment, the system comprises a processor-to-PCI bridge connected to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. A plurality of add-in board connectors are coupled to each of the generated PCI buses. In another embodiment, the system comprises two or more processor-to-PCI bridges connected to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. The resulting system expands the loading capacity of a PCI bus while adding resistance to single point failures.

Claims

1. In a computer system having a host, first, second, third, and fourth bus, a bus-to-bus bridge system comprising:

a host-to-first bi-directional bridge connecting the host bus to the first bus;

a host-to-second bi-directional bridge connecting the host bus to the second bus;

a plurality of first-to-third bi-directional bridges connecting the first bus to the third bus;

a plurality of second-to-fourth bi-directional bridges connecting the second bus to the fourth bus, wherein the plurality of first-to-third bi-directional bridges are configured to be symmetric to and perform substantially the same function as the plurality of second-to-fourth bi-directional bridges; and

a plurality of board connectors coupled to each of the first-to-third and second-to-fourth bi-directional bridges via a plurality of respective buses.

2. The system as defined in claim 1, wherein each of said first and second buses is a peripheral component interconnect (PCI) bus.

3. The system as defined in claim 1, wherein each of said plurality of respective buses is a peripheral component interconnect (PCI) bus.

4. The system as defined in claim 1, wherein each of said host-to-first and host-to-second bi-directional bridges is a processor-to-PCI bridge.

5. The system as defined in claim 1, wherein said first-to-third and second-to-fourth bi-directional bridges is a PCI-to-PCI bridge.

6. The system as defined in claim 1, wherein said plurality of first-to-third bi-directional bridges comprises four first-to-third bi-directional bridges.

7. The system as defined in claim 1, wherein said plurality of second-to-fourth bi-directional bridges comprises four second-to-third bi-directional bridges.

8. The system as defined in claim 1, wherein said plurality of board connectors comprises four board connectors.

9. The system as defined in claim 1, wherein each of said plurality of respective buses is a peripheral component interconnect (PCI) bus.

10. The system as defined in claim 1, wherein each of said plurality of respective buses is coupled to either the first or second bus by a single first-to-third or a single second-to-fourth bi-directional bridge.

11. In a computer system having a host, first, and second bus, a bus-to-bus bridge system comprising:

a host-to-first means for bi-directionally connecting the host bus to the first bus;

a host-to-second means for bi-directionally connecting the host bus to the second bus;

a plurality of first means for bi-directionally connecting the first bus to a first plurality of buses, wherein said first connecting means are coupled to said host-to-first connecting means via the first bus;

a plurality of second means for bi-directionally connecting the second bus to a second plurality of buses, wherein said second connecting means are coupled to said host-to-second connecting means via the second bus, wherein the plurality of first connecting means are symmetric to and perform substantially the same function as the plurality of second connecting means; and

a plurality of means for connecting each of the first and second plurality of buses to a plurality of boards.

12. The system as defined in claim 11, wherein each of said first and second buses is a peripheral component interconnect (PCI) bus.

13. The system as defined in claim 11, wherein each of said plurality of buses is a peripheral component interconnect (PCI) bus.

14. In a computer system having a first, second, and third bus, a bus-to-bus bridge system comprising:

a first bus-to-bus bi-directional bridge connecting the first bus to the second bus;

a first plurality of bus-to-bus bi-directional bridges connected to the second bus;

a second bus-to-bus bi-directional bridge connecting the first bus to the third bus; and

a second plurality of bus-to-bus bi-directional bridges connected to the third bus, wherein the first bus-to-bus bi-directional bridge and the first plurality of bus-to-bus bi-directional bridges are configured to be redundant to and perform substantially the same function as the second bus-to-bus bi-directional bridge and the second plurality of bus-to-bus bi-directional bridges.

15. The system as defined in claim 14, wherein the first bus-to-bus bi-directional bridge and second bus-to-bus bi-directional bridge support fault-tolerance functionality.

16. The system as defined in claim 14, wherein said system is configured such that if the first bus-to-bus bi-directional bridge fails, the second bus-to-bus bi-directional bridge maintains connectivity between the first bus and the third bus.

17. The system as defined in claim 14, wherein one of the first plurality of bus-to-bus bi-directional bridges supports a first board, and one of the second plurality of bus-to-bus bi-directional bridges supports a second board.

18. The system as defined in claim 17, wherein the first board is substantially similar to the second board.

19. The system as defined in claim 17, wherein the first board and second board are connected to a common device.

20. In a computer system having a processor bus, a first PCI bus, and a second PCI bus, a bus-to-bus bridge system comprising:

a first processor-PCI bi-directional bridge connecting the processor bus to the first PCI bus,

a second processor-PCI bi-directional bridge connecting the processor bus to the second PCI bus;

four PCI-PCI bi-directional bridges connecting the first PCI bus to a first plurality of PCI buses;

four PCI-PCI bi-directional bridges connecting the second PCI bus to a second plurality of PCI buses; and

a plurality of board connectors coupled to each of said first and second plurality of PCI buses so as to be symmetrical to and perform substantially the same function as.

21. The system as defined in claim 20, wherein said plurality of board connectors comprises four PCI board connectors.

22. The system as defined in claim 20, wherein each of the plurality of first and second PCI buses comprises four PCI buses.