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Method for supporting cache control instructions within a coherency granule

  • US 6,249,845 B1
  • Filed: 08/19/1998
  • Issued: 06/19/2001
  • Est. Priority Date: 08/19/1998
  • Status: Expired due to Fees
First Claim
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1. A method for operating a cache within a computer system including a processor, an L1 cache, and an L2 cache, wherein said L1 cache is at a higher level than said L2 cache, wherein said L2 cache has a predetermined coherency granule size within a data array, wherein said coherency granule has a plurality of MESI bits, and wherein said method comprises the steps of:

  • determining whether or not a miss has occurred in said L1 cache;

    in response to determining that a cache miss has occurred in said L1 cache, determining a state of a target sector and a state of an alternate sector within said coherency granule in said L2 cache; and

    performing a cache control instruction in conformity with said state of said target sector and said alternate sector within said coherency granule, such that said cache control instruction selectively performs a different operation on said alternate sector than is performed for said target sector.

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