IC with wait state registers

• US 6,249,859 B1
• Filed: 11/01/1999
• Issued: 06/19/2001
• Est. Priority Date: 05/04/1989
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Boutaud, Frederic, Ehlig, Peter N.
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US09/430,970
• Time in Patent Office: 596 Days
• Field of Search: 712/32, 712/40, 713/600, 713/501, 713/401, 710/16, 710/59
• US Class Current: 712/38
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test
• CPC Class Codes: G06F 11/3648 using additional hardware
• CPC Class Codes: G06F 11/3652 in-circuit-emulation [ICE] arrangements
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter

Abstract

A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Claims

1. An integrated circuit comprising:

A. a substrate of semiconductor material;

B. processor circuits formed on the substrate, the processor circuits having data pins, address pins, a control input and plural control outputs, the processor circuits being capable of receiving data at the data pins a first period of time after sending address and control signals, the processor circuits including;

i. a peripheral address bus, carrying peripheral address bus signals, connected to the address pins;

ii. a data address bus carrying data addresses;

iii. a decoder select lead carrying a decoder select signal;

iv. a data bus carrying data signals;

v. a decoder connected to at least part of the peripheral address bus, the decoder receiving at least part of the peripheral address bus signals and producing individual select signals in response to different combinations of the peripheral address bus signals, the different combinations of the peripheral address bus signals defining different segments within the peripheral memory address space, the decoder being connected to the data address bus and the decoder select lead, and the decoder producing individual select signals in response to different combinations of the data address signals during a decoder select signal;

vi. wait state registers each connected to and selected by a separate select signal, each wait state register containing a number defining a number of wait states and each wait state register having an output, each wait state register being connected to the data bus and each wait state register receiving a data signal, representing a number of wait states, from the data bus of data signals in response to a select signal from the decoder during a decoder select signal;

vii. a wait state generator connected to and receiving from a selected wait state register the number contained in that register, the generator producing a output signal corresponding to the number of wait states defined by the number in the selected wait state register; and

viii. a logic gate combining the output signal from the wait state generator with a signal on the control input to produce a wait state control signal.

2. The integrated circuit of claim 1 in which the processor circuits include multiplier circuits coupled to arithmetic and logic unit circuits.

3. The integrated circuit of claim 1 in which each wait state register corresponds to a different segment of memory external to the integrated circuit.

4. The integrated circuit of claim 1 in which the decoder is programmable to vary the programmable widths of external memory address segments.

5. The integrated circuit of claim 1 in which the number of wait states is from zero to fifteen.

6. The integrated circuit of claim 1 in which each wait state register contains at least four binary bits.