Method and system for reliability analysis of CMOS VLSI circuits based on stage partitioning and node activities

• US 6,249,898 B1
• Filed: 06/30/1998
• Issued: 06/19/2001
• Est. Priority Date: 06/30/1998
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Tuan, Jeh-Fu, Young, Tak K., Koh, Han Young
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/109,999
• Time in Patent Office: 1,085 Days
• Field of Search: 716/4, 716/5
• US Class Current: 716/109
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability

Abstract

A unique, efficient method and system for reliability simulation of a semiconductor chip design comprising millions of transistors. Specifically, the instant method starts by storing device information about a chip design as inputted. Next, by first partitioning the complex circuit of the design into numerous smaller stages, each of which confines direct current flow within its boundary, then estimating the current consumption and the relative current contribution of each transistor for each stage, the method of the present invention determines the individual currents of all power network transistors with sufficient accuracy for reliability simulation. The instant method then uses the individual transistor currents and the stored device information, including data of an accurate resistor-capacitor model of the power network, to determine the branch currents and node voltages in all interconnect wires of the power network. Finally, the instant method reports all potential problems of the design identified based on the values of the branch currents and node voltages. As such, the present invention enables circuit designers to pinpoint where voltage drop and electro-migration may pose problems and take appropriate corrective actions before chips are fabricated and sold. Thus, the present invention provides a novel and superior method for reliability simulation over the prior art by offering much greater simulation speed and capacity over conventional reliability simulation tools while delivering highly accurate results for reliability analysis crucial to today'"'"'s deep sub-micron CMOS designs.

Claims

1. A method for performing reliability analysis of a semiconductor chip design, said method comprising the computer implemented steps of:

a) storing device information and node activity data of a circuit within said chip design, wherein said circuit comprises a power network, a plurality of power network transistors and a plurality of signal nodes;

b) partitioning said circuit into a plurality of stages, wherein each of said stages comprises a subset of said power network transistors and a subset of said signal nodes, and wherein a flow of direct current across said stages is absent;

c) estimating a current for each of said power network transistors within each of said stages using said node activity data and said device information;

d) computing node voltages and branch currents of said power network using said currents of said power network transistors; and

e) reporting potential problems of said chip design based on said node voltages and said branch currents of said power network.

2. The method as recited in claim 1 wherein said stage partitioning is achieved by performing a plurality of depth-first searches (DFS) on said power network transistors, wherein a boundary between two of said stages is established whenever one of VDD, GND, a gate node of a transistor of said circuit and a pad of said circuit is encountered during one of said DFS.

3. The method as recited in claim 2 wherein said stage partitioning comprises the steps of:

b1) identifying said power network transistors in said circuit;

b2) creating one of said stages for one of said power network transistors, wherein said one power network transistor is unassigned;

and

b3) performing said DFS from a source node of said unassigned power network transistor of said step b2);

wherein those of said power network transistors and said signal nodes which are encountered during said DFS of said step b3) are assigned to said stage created in said step b2); and

wherein said steps b2) and b3) are repeated until each of said power network transistors has been assigned to one of said stages.

4. The method as recited in claim 1 wherein said step c) comprises the steps of:

c1) determining a current driving capacity (CDC) for each of said power network transistors;

c2) computing an average current for each of said stages; and

c3) assigning portions of said average current of one of said stages among said power network transistors within said stage using said current driving capacities of said power network transistors, and wherein said step c3) is performed for each of said stages.

5. The method as recited in claim 4 wherein said step c1) comprises the steps of:

c1a) identifying a maximum drain-to-source current for one of said power network transistors using said device information;

c1b) determining a toggle count for said gate node of said power network transistor of said step c1a); and

c1c) computing said CDC of said power network transistor of said step c1a) using said maximum drain-to-source current and said toggle count for said gate node of said power network transistor;

wherein said steps c1a), c1b) and c1c) are repeated until said CDC of each of said power network transistors has been computed.

6. The method as recited in claim 5 wherein said step c1b) comprises the steps of:

c1b1) looking up a first value for said toggle count for said gate node from said node activity data;

c1b2) computing a second value for said toggle count for said gate node, provided that said lookup of said first value in said step c1b1) is unsuccessful;

c1b3) returning said first value as said toggle count for said gate node, provided that said lookup of said first value in said step c1b1) is successful; and

c1b4) returning said second value as said toggle count for said gate node, provided that said lookup of said first value in said step c1b1) is unsuccessful.

7. The method as recited in claim 6 wherein said step c1b2) comprises the steps of:

identifying that particular one of said stages to which said gate node is assigned;

identifying all principal inputs of said stage;

computing a sum by adding up said toggle counts of said principal inputs of said stage; and

designating said sum as said second value of said toggle count for said gate node.

8. The method as recited in claim 4 wherein said step c2) comprises the steps of:

c2a) computing a charge injected into each of said signal nodes of one of said stages during a simulation period using said device information;

c2b) computing a total charge injected into said stage during said simulation period by adding up said charges injected into said signal nodes of said stage; and

c2c) computing said average current for said stage using said total charge injected into said stage and said simulation period;

wherein said steps c2a), c2b) and c2c) are repeated until said average current of each of said stages in said circuit has been computed.

9. The method as recited in claim 4 wherein said step c3) comprises the steps of:

c3a) computing a ratio by adding up said CDC of said power network transistors in one of said stages;

c3b) computing a transistor current for each of said power network transistors in said stage and a slack current for said stage using said ratio, said maximum drain-to-source currents of said power network transistors and said average current of said stage; and

c3c) adjusting said transistor currents of said power network transistors in said stage by apportioning said slack current of said stage among said power network transistors based on said CDC of said power network transistors, provided that said slack current for said stage is non-zero;

wherein said steps c3a), c3b) and c3c) are repeated until said transistor current has been assigned, and adjusted when determined to be necessary by said step c3c), for each of said power network transistors in each of said stages in said circuit.

10. The method as recited in claim 9 wherein said step c3b) comprises the steps of:

c3bl) calculating a first estimate for said transistor current for one of said power network transistors in said stage using said ratio and said average current of said stage;

c3b2) adding to said slack current for said stage an amount by which said first estimate for said transistor current exceeds said maximum drain-to-source current of said power network transistor, provided that said first estimate for said transistor current is larger than said maximum drain-to-source current of said power network transistor; and

c3b3) assigning a second estimate for said transistor current to said power network transistor, wherein said second estimate for said transistor current is a smaller one of said first estimate for said transistor current and said maximum drain-to-source current of said power network transistor;

wherein said steps c3b1), c3b2) and c3b3) are repeated until said second estimate for said transistor current has been assigned to each of said power network transistors in said stage.

11. The method as recited in claim 9 wherein said step c3c) comprises the steps of:

c3c1) sorting said power network transistors in said stage in descending order of said CDC of said power network transistors;

c3c2) determining a portion of said slack current for said stage attributable to that particular one of said power network transistors which is next according to said sorted order;

c3c3) comparing said portion of said slack current as determined in said step c3c2) with said slack current;

c3c4) incrementing said transistor current of said power network transistor by said portion of said slack current as determined in said step c3c2), provided that said portion of said slack current is smaller than said slack current;

c3c5) incrementing said transistor current of said power network transistor by said slack current, provided that said portion of said slack current is not smaller than said slack current; and

c3c6) decrementing said slack current by said increment to said transistor current of said power network transistor;

wherein said steps c3c1) through c3c6) are repeated until said slack current for said stage has been eliminated.

12. The method as recited in claim 1 wherein said potential problems comprise electro-migration and voltage drop violations.

13. The method as recited in claim 1 further comprising the step of:

f) presenting graphically said potential problems of said chip design using a graphical chip viewer.

14. A computer system comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit coupled to communicate with said processor, said memory unit containing instructions that when executed implement a method for reliability analysis of a semiconductor chip design, said method comprising the computer implemented steps of:

a) storing device information and node activity data of a circuit within said chip design, wherein said circuit comprises a power network, a plurality of power network transistors and a plurality of signal nodes;

b) partitioning said circuit into a plurality of stages, wherein each of said stages comprises a subset of said power network transistors and a subset of said signal nodes, and wherein a flow of direct current across said stages is absent;

c) estimating a current for each of said power network transistors within each of said stages using said node activity data and said device information;

d) computing node voltages and branch currents of said power network using said currents of said power network transistors; and

e) reporting potential problems of said chip design based on said node voltages and said branch currents of said power network.

15. The computer system as recited in claim 14 wherein said stage partitioning is achieved by performing a plurality of depth-first searches (DFS) on said power network transistors, wherein a boundary between two of said stages is established whenever one of VDD, GND, a gate node of a transistor of said circuit and a pad of said circuit is encountered during one of said DFS.

16. The computer system as recited in claim 15 wherein said stage partitioning comprises the steps of:

b1) identifying said power network transistors in said circuit;

b2) creating one of said stages for one of said power network transistors, wherein said one power network transistor is unassigned;

and

b3) performing said DFS from a source node of said unassigned power network transistor of said step b2);

wherein those of said power network transistors and said signal nodes which are encountered during said DFS of said step b3) are assigned to said stage created in said step b2); and

wherein said steps b2) and b3) are repeated until each of said power network transistors has been assigned to one of said stages.

17. The computer system as recited in claim 14 wherein said step c) comprises the steps of:

c1) determining a current driving capacity (CDC) for each of said power network transistors;

c2) computing an average current for each of said stages; and

c3) assigning portions of said average current of one of said stages among said power network transistors within said stage using said current driving capacities of said power network transistors, and wherein said step c3) is performed for each of said stages.

18. The computer system as recited in claim 17 wherein said step c1) comprises the steps of:

c1a) identifying a maximum drain-to-source current for one of said power network transistors using said device information;

c1b) determining a toggle count for said gate node of said power network transistor of said step c1a); and

c1c) computing said CDC of said power network transistor of said step c1a) using said maximum drain-to-source current and said toggle count for said gate node of said power network transistor;

wherein said steps c1a), c1b) and c1c) are repeated until said CDC of each of said power network transistors has been computed.

19. The computer system as recited in claim 18 wherein said step c1b) comprises the steps of:

c1b1) looking up a first value for said toggle count for said gate node from said node activity data;

c1b2) computing a second value for said toggle count for said gate node, provided that said lookup of said first value in said step c1b1) is unsuccessful;

c1b3) returning said first value as said toggle count for said gate node, provided that said lookup of said first value in said step c1b1) is successful; and

c1b4) returning said second value as said toggle count for said gate node, provided that said lookup of said first value in said step c1b1) is unsuccessful.

20. The computer system as recited in claim 19 wherein said step c1b2) comprises the steps of:

identifying that particular one of said stages to which said gate node is assigned;

identifying all principal inputs of said stage;

computing a sum by adding up said toggle counts of said principal inputs of said stage; and

designating said sum as said second value of said toggle count for said gate node.

21. The computer system as recited in claim 17 wherein said step c2) comprises the steps of:

c2a) computing a charge injected into each of said signal nodes of one of said stages during a simulation period using said device information;

c2b) computing a total charge injected into said stage during said simulation period by adding up said charges injected into said signal nodes of said stage; and

c2c) computing said average current for said stage using said total charge injected into said stage and said simulation period;

wherein said steps c2a), c2b) and c2c) are repeated until said average current of each of said stages in said circuit has been computed.

22. The computer system as recited in claim 17 wherein said step c3) comprises the steps of:

c3a) computing a ratio by adding up said CDC of said power network transistors in one of said stages;

c3b) computing a transistor current for each of said power network transistors in said stage and a slack current for said stage using said ratio, said maximum drain-to-source currents of said power network transistors and said average current of said stage; and

c3c) adjusting said transistor currents of said power network transistors in said stage by apportioning said slack current of said stage among said power network transistors based on said CDC of said power network transistors, provided that said slack current for said stage is non-zero;

wherein said steps c3a), c3b) and c3c) are repeated until said transistor current has been assigned, and adjusted when determined to be necessary by said step c3c), for each of said power network transistors in each of said stages in said circuit.

23. The computer system as recited in claim 22 wherein said step c3b) comprises the steps of:

c3b1) calculating a first estimate for said transistor current for one of said power network transistors in said stage using said ratio and said average current of said stage;

c3b2) adding to said slack current for said stage an amount by which said first estimate for said transistor current exceeds said maximum drain-to-source current of said power network transistor, provided that said first estimate for said transistor current is larger than said maximum drain-to-source current of said power network transistor; and

c3b3) assigning a second estimate for said transistor current to said power network transistor, wherein said second estimate for said transistor current is a smaller one of said first estimate for said transistor current and said maximum drain-to-source current of said power network transistor;

wherein said steps c3b1), c3b2) and c3b3) are repeated until said second estimate for said transistor current has been assigned to each of said power network transistors in said stage.

24. The computer system as recited in claim 22 wherein said step c3c) comprises the steps of:

c3c1) sorting said power network transistors in said stage in descending order of said CDC of said power network transistors;

c3c2) determining a portion of said slack current for said stage attributable to that particular one of said power network transistors which is next according to said sorted order;

c3c3) comparing said portion of said slack current as determined in said step c3c2) with said slack current;

c3c4) incrementing said transistor current of said power network transistor by said portion of said slack current as determined in said step c3c2), provided that said portion of said slack current is smaller than said slack current;

c3c5) incrementing said transistor current of said power network transistor by said slack current, provided that said portion of said slack current is not smaller than said slack current; and

c3c6) decrementing said slack current by said increment to said transistor current of said power network transistor;

wherein said steps c3c1) through c3c6) are repeated until said slack current for said stage has been eliminated.

25. The computer system as recited in claim 14 wherein said potential problems comprise electro-migration and voltage drop violations.

26. The computer system as recited in claim 14 further comprising the step of:

f) presenting graphically said potential problems of said chip design using a graphical chip viewer.

27. In a device for reliability analysis of a semiconductor chip design, a computer-usable medium having computer-readable program code embodied therein for causing a computer to perform the steps of:

a) storing device information and node activity data of a circuit within said chip design, wherein said circuit comprises a power network, a plurality of power network transistors and a plurality of signal nodes;

b) partitioning said circuit into a plurality of stages, wherein each of said stages comprises a subset of said power network transistors and a subset of said signal nodes, and wherein a flow of direct current across said stages is absent;

c) estimating a current for each of said power network transistors within each of said stages using said node activity data and said device information;

d) computing node voltages and branch currents of said power network using said currents of said power network transistors; and

e) reporting potential problems of said chip design based on said node voltages and said branch currents of said power network.

28. The computer-usable medium as recited in claim 27 wherein said stage partitioning is achieved by performing a plurality of depth-first searches (DFS) on said power network transistors, wherein a boundary between two of said stages is established whenever one of VDD, GND, a gate node of a transistor of said circuit and a pad of said circuit is encountered during one of said DFS.

29. The computer-usable medium as recited in claim 28 wherein said stage partitioning comprises the steps of:

b1) identifying said power network transistors in said circuit;

b2) creating one of said stages for one of said power network transistors, wherein said one power network transistor is unassigned; and

b3) performing said DFS from a source node of said unassigned power network transistor of said step b2);

wherein those of said power network transistors and said signal nodes which are encountered during said DFS of said step b3) are assigned to said stage created in said step b2); and

wherein said steps b2) and b3) are repeated until each of said power network transistors has been assigned to one of said stages.

30. The computer-usable medium as recited in claim 27 wherein said step c) comprises the steps of:

c1) determining a current driving capacity (CDC) for each of said power network transistors;

c2) computing an average current for each of said stages; and

c3) assigning portions of said average current of one of said stages among said power network transistors within said stage using said current driving capacities of said power network transistors, and wherein said step c3) is performed for each of said stages.

31. The computer-usable medium as recited in claim 30 wherein said step c1) comprises the steps of:

c1a) identifying a maximum drain-to-source current for one of said power network transistors using said device information;

c1b) determining a toggle count for said gate node of said power network transistor of said step c1a); and

c1c) computing said CDC of said power network transistor of said step c1a) using said maximum drain-to-source current and said toggle count for said gate node of said power network transistor;

wherein said steps c1a), c1b) and c1c) are repeated until said CDC of each of said power network transistors has been computed.

32. The computer-usable medium as recited in claim 31 wherein said step c1b) comprises the steps of:

c1b1) looking up a first value for said toggle count for said gate node from said node activity data;

c1b2) computing a second value for said toggle count for said gate node, provided that said lookup of said first value in said step c1b1) is unsuccessful;

c1b3) returning said first value as said toggle count for said gate node, provided that said lookup of said first value in said step c1b1) is successful; and

c1b4) returning said second value as said toggle count for said gate node, provided that said lookup of said first value in said step c1b1) is unsuccessful.

33. The computer-usable medium as recited in claim 32 wherein said step c1b2) comprises the steps of:

identifying that particular one of said stages to which said gate node is assigned;

identifying all principal inputs of said stage;

computing a sum by adding up said toggle counts of said principal inputs of said stage; and

designating said sum as said second value of said toggle count for said gate node.

34. The computer-usable medium as recited in claim 30 wherein said step c2) comprises the steps of:

c2a) computing a charge injected into each of said signal nodes of one of said stages during a simulation period using said device information;

c2b) computing a total charge injected into said stage during said simulation period by adding up said charges injected into said signal nodes of said stage; and

c2c) computing said average current for said stage using said total charge injected into said stage and said simulation period;

wherein said steps c2a), c2b) and c2c) are repeated until said average current of each of said stages in said circuit has been computed.

35. The computer-usable medium as recited in claim 30 wherein said step c3) comprises the steps of:

c3a) computing a ratio by adding up said CDC of said power network transistors in one of said stages;

c3b) computing a transistor current for each of said power network transistors in said stage and a slack current for said stage using said ratio, said maximum drain-to-source currents of said power network transistors and said average current of said stage; and

c3c) adjusting said transistor currents of said power network transistors in said stage by apportioning said slack current of said stage among said power network transistors based on said CDC of said power network transistors, provided that said slack current for said stage is non-zero;

wherein said steps c3a), c3b) and c3c) are repeated until said transistor current has been assigned, and adjusted when determined to be necessary by said step c3c), for each of said power network transistors in each of said stages in said circuit.

36. The computer-usable medium as recited in claim 35 wherein said step c3b) comprises the steps of:

c3b1) calculating a first estimate for said transistor current for one of said power network transistors in said stage using said ratio and said average current of said stage;

c3b2) adding to said slack current for said stage an amount by which said first estimate for said transistor current exceeds said maximum drain-to-source current of said power network transistor, provided that said first estimate for said transistor current is larger than said maximum drain-to-source current of said power network transistor; and

c3b3) assigning a second estimate for said transistor current to said power network transistor, wherein said second estimate for said transistor current is a smaller one of said first estimate for said transistor current and said maximum drain-to-source current of said power network transistor;

wherein said steps c3b1), c3b2) and c3b3) are repeated until said second estimate for said transistor current has been assigned to each of said power network transistors in said stage.

37. The computer-usable medium as recited in claim 35 wherein said step c3c) comprises the steps of:

c3c1) sorting said power network transistors in said stage in descending order of said CDC of said power network transistors;

c3c2) determining a portion of said slack current for said stage attributable to that particular one of said power network transistors which is next according to said sorted order;

c3c3) comparing said portion of said slack current as determined in said step c3c2) with said slack current;

c3c4) incrementing said transistor current of said power network transistor by said portion of said slack current as determined in said step c3c2), provided that said portion of said slack current is smaller than said slack current;

c3c5) incrementing said transistor current of said power network transistor by said slack current, provided that said portion of said slack current is not smaller than said slack current; and

c3c6) decrementing said slack current by said increment to said transistor current of said power network transistor;

wherein said steps c3c1) through c3c6) are repeated until said slack current for said stage has been eliminated.

38. The computer-usable medium as recited in claim 27 wherein said potential problems comprise electro-migration and voltage drop violations.

39. The computer-usable medium as recited in claim 27 further comprising the step of:

f) presenting graphically said potential problems of said chip design using a graphical chip viewer.