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Method and apparatus for generating and maintaining electrical modeling data for a deep sub-micron integrated circuit design

  • US 6,249,903 B1
  • Filed: 03/31/1998
  • Issued: 06/19/2001
  • Est. Priority Date: 03/31/1998
  • Status: Expired due to Term
First Claim
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1. A machine readable storage medium having stored therein a plurality of machine executable instructions that implement a parasitic extraction tool to generate electrical modeling data for an integrated circuit (IC) design, wherein the parasitic extraction tool includes a read function to input extracted connectivity and geometrical data of various layout nets of the IC design from at least one filtered database, said connectivity and geometric data having been filtered based at least in part on parasitic effect windows of respective layout layers, wherein a particular parasitic effect window defines a distance from geometric shapes on a given layout layer beyond which parasitic effects are ignored.

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