Method to plate C4 to copper stud

• US 6,251,528 B1
• Filed: 01/09/1998
• Issued: 06/26/2001
• Est. Priority Date: 01/09/1998
• Status: Expired due to Fees

• Current Assignee: Ultratech Incorporated (Veeco Instruments Incorporated)
• Original Assignee: International Business Machines Corporation
• Inventors: Edelstein, Daniel C., Uzoh, Cyprian Emeka
• Primary Examiner(s): Gorgos, Kathryn
• Assistant Examiner(s): MAISANO, JOSEPHINE R
• Application Number:
  US09/004,808
• Time in Patent Office: 1,264 Days
• Field of Search: 205/149, 205/159, 428/587-596
• US Class Current: 428/587
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03602 Mechanical treatment, e.g. polishing, grinding
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10T 428/12299 : Workpiece mimicking finished stock having nonrectangular or noncircular cross section
• CPC Class Codes: Y10T 428/12361 : having aperture or cut

Abstract

A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate;

at least one metal feature provided in said substrate;

at least one insulating layer at least partially covering said at least one metal feature;

at least one recess located in said at least one insulating layer over said at least one metal feature;

at least one conductive barrier layer located over said at least one electrical insulating layer and over a portion of said at least one metal feature under said at least one recess, said conductive barrier layer comprising at least one nitride of tantalum and α

-phase tantalum;

at least one plating seed layer of a first metal located over a portion of said conductive barrier layer within said at least one recess, said seed layer and barrier layer in combination forming a continuous conductive layer; and

a second metal electroplated to said seed layer within said at least one recess.

2. The semiconductor structure according to claim 1, wherein said at least one metal feature is formed of at least one metal or alloy having low resistivity.

3. The semiconductor structure according to claim 2, wherein said metal or alloy includes at least one member selected from the group consisting of Al, Au, Ni, W, α

-Ta, and alloys including Al, Au, Ni, W, or α

-Ta.

4. The semiconductor structure according to claim 1, wherein the barrier layer further comprises a layer of tantalum on the tantalum nitride layer.

5. The semiconductor structure according to claim 4, wherein the tantalum nitride layer is about 10 Å

to about 1000 Å

thick and the tantalum layer is about 500 Å

to about 5000 Å

thick.

6. The semiconductor structure according to claim 4, wherein the barrier layer comprises a TaN/α

-Ta/TaN-laminate.

7. The semiconductor structure according to claim 1, wherein the seed layer comprises copper.

8. The semiconductor structure according to claim 7, wherein the barrier layer comprises tantalum and barrier and seed layers comprise α

-Ta/TaN/Cu.

9. The semiconductor structure according to claim 7, wherein said copper layer is about 1000 Å

to about 20,000 Å

thick.

10. The semiconductor structure according to claim 1, wherein the barrier layer forms a conductor for electroplating of the second metal.

11. The semiconductor structure according to claim 1, wherein the second metal comprises a solder ball comprising an alloy of lead and tin, plated lead-free solder or other platable terminal metallurgies.

12. The semiconductor structure according to claim 1, wherein the second metal is a solder ball.

13. The semiconductor structure according to claim 1, wherein said the layer comprises a layer of an oxide and a nitride and at least one layer of a polyimide.

14. The semiconductor structure according to claim 13, further comprising:

a layer of at least one nitride or other passivation layer over the polyimide.