Semiconductor power device manufacture

• US 6,251,730 B1
• Filed: 07/07/1999
• Issued: 06/26/2001
• Est. Priority Date: 07/11/1998
• Status: Expired due to Term

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Luo, JiKui
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US09/348,960
• Time in Patent Office: 720 Days
• Field of Search: 438/270, 438/271, 438/268, 438/272, 438/589, 438/596, 438/564, 257/330
• US Class Current: 438/270
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In the manufacture of a semiconductor power device such as a trench-gate power MOSFET, a source region (13) is formed using a sidewall extension (30) of an upstanding insulated-gate structure (11,21,22). The sidewall extension (30) forms a step with an adjacent surface area (10a′) of a body region (15) of a first conductivity type and comprises doped semiconductor material (13a) of opposite, second conductivity type which is separated from the gate (11) by insulating material (22). The body region (15) provides a channel-accommodating portion (15a) adjacent to the gate structure (11,21,22) and also comprises a localised high-doped portion (15b) which extends to a greater depth in the semiconductor body (10) than the shallow p-n junction between the source region (13) and the channel-accommodating portion (15a), and preferably deeper even than the bottom of the trench (20) of a trench-gate device. This high-doped portion (15b) is formed by introducing dopant of the first conductivity type into the semiconductor body (10) via the stepped-down adjacent surface area (10a′) while using the stepped-up sidewall extension (30) comprising the doped source region material (13a) to mask the underlying channel area. Source electrode material (33) is deposited over the step so as to contact the doped semiconductor material (13a) of the sidewall extension (30) and the adjacent surface area (10a′) of the high-doped portion (15b).

Claims

1. A method of manufacturing a semiconductor power device having a trench-gate capacitively coupled to a channel-accommodating portion of a body region of a first conductivity type, including the steps of:

(a) providing at a major surface of a semiconductor body where the body region is provided a mask that comprises a thicker second layer of a second material on a thinner first layer of an oxidation-masking first material, the mask having a window where the trench-gate is to be provided in the semiconductor body,

(b) etching a trench in the semiconductor body at the window,

(c) providing the trench-gate in the trench and in the window by steps that include depositing doped semiconductor gate material on the mask and in the window and etching away the doped semiconductor gate material from on top of the mask,

(d) removing the second layer from the mask and then etching back the doped semiconductor gate material from sides of the window in the first layer so as to leave the doped semiconductor gate material freely upstanding within the window,

(e) oxidising an upper part of the doped semiconductor gate material, while using the first layer as an oxidation mask, so as to form an upstanding insulated gate structure that has an insulating overlayer and that protrudes above the major surface of the semiconductor body,

(f) removing the first layer and then forming a sidewall extension at upstanding sides of the insulated gate structure so as to form a step with an adjacent surface area of the body region of the first conductivity type, the sidewall extension comprising doped semiconductor material of opposite, second conductivity type which is insulated from the trench-gate and which provides a source region of the device, the source region forming a p-n junction with the channel-accommodating portion,

(g) introducing dopant of the first conductivity type into the semiconductor body via the said adjacent surface area while using the sidewall extension to mask an underlying area of the semiconductor body, and thereby to provide the body region with a localised high-doped portion that has a doping concentration of the first conductivity type which is higher than that of the channel-accommodating portion but lower than the conductivity-determining dopant concentration of the doped semiconductor material of the sidewall extension that provides the source region, which high-doped portion is provided to a greater depth in the semiconductor body than the p-n junction between the source region and the channel-accommodating portion of the body region, and

(h) depositing a source electrode over the step so as to contact the doped semiconductor material of the sidewall extension and the high-doped portion of the body region at the adjacent surface area of the semiconductor body.

2. A method as claimed in claim 1, further characterised in that the depositing step further comprises doped semiconductor source material of the second conductivity type deposited on the gate structure and on the body region of the first conductivity type at said major surface and is etched back to leave the sidewall extension as the source region.

3. A method as claimed in claim 2, further characterised in that dopant from the doped semiconductor source material of the sidewall extension is diffused into the semiconductor body by heating the semiconductor body to a dopant diffusion temperature, so as to move the p-n junction between the source region and the channel-accommodating portion away from the interface of the deposited doped semiconductor material and the major surface of the semiconductor body.

4. A method as claimed in claim 1, further characterised in that the doped semiconductor material of the sidewall extension comprises silicon, the semiconductor body at least adjacent to said major surface comprises silicon, and in that the method further comprises depositing a silicide-forming metal to form a low-resistance silicide contact both to the doped semiconductor material of the sidewall extension and to the adjacent surface area of the high-doped portion before depositing a main electrode material for the source electrode.

5. A method as claimed in claim 1, further characterised in that the method further comprises forming the doped semiconductor material of the sidewall extension by etching into said major surface of the body through a surface region of the second conductivity type adjacent said major surface while masking an area of said surface region adjacent to the gate structure to form the source region.

6. A method as claimed in claim 5, further characterised in that a masking pattern which masks said area of said surface region to form the source region is present as part of the sidewall extension when the dopant introduction for forming the localised high-doped portion is effected.

7. A method as claimed in claim 1, further characterised in that the method further comprises providing the localised high-doped portion to a greater depth in the semiconductor body than the channel-accommodating portion.

8. A method as claimed in claim 1, further characterised in that the method further comprises implanting the dopant of said first conductivity type for forming the localised high-doped portion into the semiconductor body while using the sidewall extension as an implantation mask over the underlying area of the body.

9. In a method of manufacturing a trench-gate semiconductor device having a channel-accommodating region adjacent to an insulated trench-gate structure, the insulated trench-gate structure is formed by steps that include:

etching a trench in a semiconductor body at a window in a mask at a major surface of the semiconductor body, the mask comprising a thicker second layer of a second material on a thinner first layer of an oxidation-masking first material,

depositing doped semiconductor gate material on the mask and in the window for providing the trench-gate,

removing the doped semiconductor gate material from on top of the mask and removing the second layer of the mask so as to leave the doped semiconductor gate material upstanding in the trench and in the window in the first layer of the mask,

etching back the doped semiconductor gate material from sides of the window in the first layer so as to leave an upper part of the doped semiconductor gate material freely upstanding within the window in the first layer, and

forming an insulating layer at the freely upstanding upper part of the doped semiconductor gate material by oxidation while using the first layer to mask an adjacent surface area of the body.

10. A method as claimed in claim 9, wherein the channel-accommodating region of the device is provided as a region of a first conductivity type in the semiconductor body, and wherein, after forming the insulating layer at the freely upstanding upper part of the doped semiconductor gate material, the first layer of the mask is removed and a sidewall extension comprising doped semiconductor material of opposite, second conductivity type is formed at upstanding sides of the trench-gate structure, which sidewall extension provides a source region of the device that is separated from the trench-gate by the insulating layer.