Process for polycrystalline silicon gates and high-K dielectric compatibility

• US 6,251,761 B1
• Filed: 11/22/1999
• Issued: 06/26/2001
• Est. Priority Date: 11/24/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Rodder, Mark S., Hattangady, Sunil V.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): PHAM, THANHHA S
• Application Number:
  US09/447,175
• Time in Patent Office: 582 Days
• Field of Search: 438/240, 438/287, 438/216, 438/591, 438/761, 438/785, 438/197, 438/199, 438/217, 438/229, 438/230, 438/231, 438/263, 438/262, 438/261, 438/257, 438/266, 438/592, 438/584
• US Class Current: 438/591
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A gate stack (104) including a gate dielectric with reduced effective electrical thickness. A high-k dielectric (108) is formed over the silicon substrate (102). Remote plasma nitridation of the high-k dielectric is performed to create a nitride layer (107) over the high-k dielectric (107). A conductive layer (110) is formed over the nitride layer (107) forming the gate electrode.

Claims

1. A method of fabricating an integrated circuit MOSFET transistor, comprising the steps of:

forming a dielectric layer with an upper surface over a semiconductor body;

forming a high-K dielectric layer with an upper surface over said dielectric layer;

subjecting said high-K dielectric layer to a remote plasma nitridation to convert said upper surface of the high-K dielectric to a nitride layer;

forming a conductive layer on said nitride layer;

patterning and etching said conductive layer, said high-K dielectric layer, said dielectric layer and said nitride layer to form a gate stack;

forming drain extension regions in said semiconductor body adjacent said gate stack;

forming sidewall spacers over said semiconductor body adjacent said gate stack; and

forming source/drain regions in said semiconductor body adjacent said sidewall spacers.

2. The method of claim 1 wherein said high-K dielectric comprises an oxygen-containing material.

3. The method of claim 1 wherein said high-K dielectric layer comprises a material selected from the group consisting of:

Ta2O5, BaTiO3, TiO2, CeO2, and BST.

4. The method of claim 1 wherein said conductive layer comprises a silicon-containing material.

5. The method of claim 1 wherein said conductive layer comprises polysilicon.

6. The method of claim 1 wherein said conductive layer comprises a metal.

7. The method of claim 1 wherein said conductive layer comprises a tungsten layer overlying a titanium-nitride layer.

8. The method of claim 1, wherein said remote plasma nitridation uses nitrogen containing precursors selected from the group consisting of N₂, NH₃, NO, and N₂O.

9. The method of claim 1, wherein said remote plasma nitridation occurs at a temperature in the range of 77 K-773 K.

10. The method of claim 1, wherein said remote plasma nitridation occurs at a pressure in the range of 1 to 50 mTorr.

11. The method of claim 1, wherein said remote plasma nitridation comprises a plasma density in the range of 1×

10¹⁰ to 1×

10¹².

12. The method of claim 1, wherein said remote plasma nitridation comprises a nitrogen flow in the range of 1 to 100 sccm.

13. The method of claim 1, wherein said remote plasma nitridation comprises a duration in the range of 10 to 60 seconds.

14. A method of fabrication an integrated circuit MOS transistor, comprising the steps of:

forming a silicon dioxide layer over a semiconductor body;

subjecting said silicon dioxide layer to a remote plasma nitridation to convert said silicon dioxide layer to a silicon-oxynitride layer;

forming a high-k dielectric layer with an upper surface over said silicon-oxynitride layer, said high-K dielectric layer having a dielectric constant greater than 10;

subjecting said high-k dielectric layer to a remote plasma nitridation to convert said upper surface of said high-k dielectric to a nitride;

forming a conductive layer over said high-K dielectric layer; and

patterning and etching said conductive layer, said high-K dielectric layer, said nitride, and said silicon oxynitride layer to form a gate stack.

15. The method of claim 14, further comprising the steps of:

forming drain extension regions in said semiconductor body adjacent said gate stack;

forming sidewall spacers over said semiconductor body adjacent said gate stack; and

forming source/drain regions in said semiconductor body adjacent said sidewall spacers.

16. The method of claim 14, wherein said silicon dioxide layer has a thickness less than 20 Angstroms.

17. The method of claim 14, wherein said high-K dielectric layer comprises an oxygen-containing material.

18. The method of claim 14, wherein said conductive layer comprises a tungsten layer overlying a titanium-nitride layer.

19. The method of claim 14, wherein said conductive layer comprises a polysilicon layer.