Method for improving attachment reliability of semiconductor chips and modules

• US 6,251,766 B1
• Filed: 09/02/1999
• Issued: 06/26/2001
• Est. Priority Date: 03/12/1997
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Desai, Kishor V., Sarkhel, Amit K.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): BEREZNY, NEMA O
• Application Number:
  US09/388,755
• Time in Patent Office: 663 Days
• Field of Search: 438/612, 438/614, 438/615, 438/616, 257/779
• US Class Current: 438/614
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 1/112 : directly combined with via connections
• CPC Class Codes: H05K 2201/09472 : Recessed pad for surface mounting; Recessed electrode of component
• CPC Class Codes: H05K 2201/09509 : Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09736 : Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
• CPC Class Codes: H05K 2201/09745 : Recess in conductor, e.g. in pad or in metallic substrate
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2201/10992 : Using different connection materials, e.g. different solders, for the same connection
• CPC Class Codes: H05K 2203/041 : Solder preforms in the shape of solder balls
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Claims

1. A process for forming an improved solder interconnection on a semiconductor device and supporting substrate comprising:

forming a raised solder wettable pad structure on said supporting substrate by depositing a first layer on said supporting substrate and depositing a second layer over said first layer, said first and second layers are substantially circular, each having a respective diameter, said diameter of said second layer is in the range of 30-70% of said diameter of said first layer, said first layer has a thickness at least 10% of said diameter of said first layer, said thickness of said first layer is in the range of 33-41 μ

m (0.0013 to 0.0016 inches) and said second layer has a thickness in the range of 63-76 μ

m (0.0025 to 0.0030 inches);

said substrate is one of the group consisting of an organic chip carrier, a ceramic chip carrier, and an organic circuit board;

depositing a layer of solder over the resultant pad structure;

placing said semiconductor device, provided with a corresponding solder wettable pad, on said supporting substrate; and

heating to join said pad on said semiconductor device to said pad structure on said substrate by reflowing said layer of solder.

2. The process according to claim 1, further comprising:

depositing a further layer of solder over said solder wettable pad on said semiconductor device and depositing a solder ball on said further layer of solder, prior to placing said semiconductor device on said supporting substrate.

3. The process according to claim 2, wherein said solder in said layer of solder and said further layer of solder comprises tin and lead, and said first layer is one of a metal and an alloy and said second layer is one of a metal and an alloy, said first layer and said second layer each comprise at least one of the group consisting of copper, cobalt, nickel platinum and palladium.

4. A method of forming a metallic contact on an integrated circuit card, comprising the steps of:

patterning and depositing a first layer on a substrate on said integrated circuit card;

patterning and depositing a second layer on said first layer to form at least one raised structure on said first layer said first and second layers are substantially circular, each having a respective diameter, said diameter of said second layer is in the range of 30-70% of said diameter of said first layer, said first layer has a thickness at least 10% of said diameter of said first layer, said thickness of said first layer is in the range of 33-41 μ

m (0.0013 to 0.0016 inches) and said second layer has a thickness in the range of 63-76 μ

m (0.0025 to 0.0030 inches) said substrate is one of the group consisting of an organic chip carrier, a ceramic chip carrier, and an organic circuit board; and

depositing solder over said raised structure and a portion of said first layer.

5. The method according to claim 4, wherein said first layer is one of a metal and an alloy and said second layer is one of a metal and an alloy, said first and second layers being solder wettable and each comprise at least one of the group consisting of copper, cobalt, nickel platinum, palladium, and alloys thereof.

6. The method according to claim 4, wherein said first layer and said second layer are patterned and deposited by at least one technique selected from the group consisting of plating, evaporation, and etching.