Method of manufacturing a semiconductor device

• US 6,251,774 B1
• Filed: 04/28/1999
• Issued: 06/26/2001
• Est. Priority Date: 11/10/1998
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Harada, Akihiko, Saito, Takayuki
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Anya, Igwe U.
• Application Number:
  US09/300,848
• Time in Patent Office: 790 Days
• Field of Search: 438/622, 438/637, 438/624, 438/631, 438/633, 438/634, 438/638, 438/640, 438/675, 438/692, 438/701, 438/703, 438/761, 438/713, 438/948, 257/758, 257/751, 257/752, 257/759, 257/762, 257/774
• US Class Current: 438/637
• CPC Class Codes: H01L 21/02263 deposition from the gas or vapour phase
• CPC Class Codes: H01L 21/3145 formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence

Abstract

There is described a method of manufacturing a semiconductor device for the purpose of preventing damage to a lower wiring layer, wherein wiring elements of dual damascene structure are formed on the lower wiring layer. Under the method, a first silicon nitride film, a first silicon oxide film, a second silicon nitride film, and a second silicon oxide film are formed, in this sequence, on a lower wiring layer. A via hole is formed at a position above the lower wiring layer so as to pass through the second silicon oxide film and the second silicon nitride film. A photoresist is embedded into the via hole so as to cover the internal wall surface thereof. After formation of a protective film from the photoresist, predetermined portions of the second silicon oxide film and the second silicon nitride film are removed, thus forming a wiring trench.

Claims

1. A method of manufacturing a semiconductor device having a wiring element of dual damascene structure, the method comprising the sequential steps of:

forming on a lower wiring layer a film for preventing diffusion of metal;

forming a first dielectric film on the metal diffusion prevention film;

forming an etch stopper film on the first dielectric film;

forming a second dielectric film on the etch stopper film;

forming a via hole at a position above the lower wiring layer by etching through the second dielectric film, the etch stopper film, and the first dielectric film;

forming an organic layer within the via hole so as to cover the internal wall surface of the via hole; and

forming a wiring trench after formation of the organic layer by etching a predetermined portion of the second dielectric film;

wherein the organic layer is formed so as to cover at least an area of the via hole from the bottom of the via hole to the internal surface of the second dielectric film.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming an organic layer comprises the steps of:

filling the via hole with photoresist; and

setting the photoresist.

3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming an organic layer comprises a step of forming, inside the via hole, a layer of organic antireflective agent as the organic layer.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a lower wiring layer comprises the steps of:

forming an etch stopper film on a silicon substrate;

forming a base dielectric film on the etch stopper film;

forming a lower wiring trench through photolithography and anisotropic etching;

filling the lower wiring trench with primary metal material after a high-melting-point metal film has been formed in the lower wiring trench;

removing an excessive primary metal material that exists outside of the lower wiring trench; and

forming a high-melting-point metal film on the primary metal material.

5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of filling the lower wiring trench with primary metal material and then smoothing the lower wiring trench until the surface of the base dielectric film becomes exposed and the primary metal material that exists outside the lower wiring trench disappears, and

wherein the step of forming a high-melting-point metal film comprises the steps of:

forming a high-melting-point metal layer at a position above the silicon substrate and the primary metal material; and

etching away the high-melting-point metal layer such that the high-melting-point metal layer is left only in a predetermined location where it covers the primary metal film.

6. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of recessing the surface of the primary metal material which has been filled in the lower wiring trench, so that the primary metal material becomes lower than the surface of the base dielectric film by a predetermined depth, and

wherein the step of forming a high-melting-point metal film comprises the steps of:

forming a high-melting-point metal layer at a position above the base dielectric film and the primary metal material after the surface of the primary metal material has been recessed; and

removing the high-melting-point metal film until the surface of the base dielectric film becomes exposed such that the high-melting-point metal layer is left only at a predetermined location where it covers the primary metal film.

7. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a lower wiring layer comprises the steps of:

forming a lower wiring trench in the base dielectric film;

filling the lower wiring trench with primary metal material after formation of a high-melting-point metal film in the lower wiring trench; and

forming, on the primary metal material, a silicon nitride film having an absorption factor of 0.5 to 1.0.

8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of filling the lower wiring trench with primary metal material and then smoothing the surface of the base dielectric film and the surface of the primary metal material, and

wherein the step of forming a silicon nitride film comprises the steps of:

forming a silicon nitride layer having an absorption factor of 0.5 to 1.0 on the silicon substrate and the primary metal; and

etching the silicon nitride layer such that the silicon nitride layer exists only at a predetermined location where it covers the primary metal film.

9. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of recessing the surface of the primary metal material which has been filled in the lower wiring trench, so that the surface of the primary metal material becomes lower than the surface of the base dielectric film by a predetermined depth, and

wherein the step of forming a silicon nitride film comprises the steps of:

forming a silicon nitride layer at a position above the silicon substrate and the primary metal material after the surface of the primary metal material has been recessed; and

removing the silicon nitride layer until the surface of the base dielectric film becomes exposed such that the silicon nitride layer is left only at a position where it covers the primary metal film.

10. The method of manufacturing a semiconductor device according to claim 1, wherein the etch stopper film includes a silicon nitride film having an absorption factor of 0.5 to 1.0.

11. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a via hole comprises the steps of:

growing a first organic antireflective film at a position above the second dielectric film; and

forming, at a position above the first organic antireflective film, a first photoresist film so that the first photoresist film has an opening at a position corresponding to the via hole, and

wherein the step of forming a wiring trench comprises the steps of;

growing a second organic antireflective film on the second dielectric film, and

forming, at a position above the second organic antireflective film, a second photoresist film that has an opening corresponding to the wiring trench.

12. The method according to claim 1, comprising forming the via hole by:

first etching through the second dielectric film stopping on and exposing the etch stopper film;

then etching through the etch stopper film stopping on and exposing the first dielectric film; and

then etching through the first dielectric film.

13. A method of manufacturing a semiconductor device having a wiring element of dual damascene structure, the method comprising the sequential steps of:

forming on a lower wiring layer a film for preventing diffusion of metal;

forming a first dielectric film on the metal diffusion prevention film;

forming an etch stopper film on the first dielectric film;

forming a second dielectric film on the etch stopper film;

forming a via hole at a position above the lower wiring layer by etching through the second dielectric film, the etch stopper film, and the first dielectric film;

forming an organic layer within the via hole so as to cover the internal wall surface of the via hole;

forming a wiring trench after formation of the organic layer by etching away a predetermined portion of the second dielectric film;

forming an antireflective high-melting-point metal film at a position above the second dielectric film before opening of the via hole; and

removing the antireflective high-melting-point metal film that exists at the position above the second dielectric film after formation of the wiring trench,

wherein the step of forming a via hole comprises a step of removal of the portion of the antireflective high-melting-point metal film that corresponds to the via hole, and

wherein the step of forming a wiring trench comprises a step of removal of the portion of the antireflective high-melting-point metal film that corresponds to the wiring trench.

14. A method of manufacturing a semiconductor device having a wiring element of dual damascene structure, the method comprising the sequential steps of:

forming on a lower wiring layer a film for preventing diffusion of metal;

forming a first dielectric film on the metal diffusion prevention film;

forming an etch stopper film on the first dielectric film;

forming a second dielectric film on the etch stopper film;

forming a via hole at a position above the lower wiring layer by etching through the second dielectric film, the etch stopper film, and the first dielectric film;

forming an organic layer within the via hole so as to cover the internal wall surface of the via hole;

forming a wiring trench after formation of the organic layer by etching away a predetermined portion of the second dielectric film;

forming an antireflective silicon nitride film having an absorption factor of 0.5 to 1.0 at a position above the second dielectric film before opening of the via hole; and

removing the antireflective silicon nitride film that exists at the position above the second dielectric film after formation of the wiring trench,

wherein the step of forming a via hole comprises a step of removal of the portion of the antireflective silicon nitride film that corresponds to the via hole, and

wherein the step of forming a wiring trench comprises a steps of removal of the portion of the antireflective silicon nitride film that corresponds to the wiring trench.