Thin film transistor and display

• US 6,252,248 B1
• Filed: 06/07/1999
• Issued: 06/26/2001
• Est. Priority Date: 06/08/1998
• Status: Expired due to Term

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamada, Tsutomu, Segawa, Yasuo, Sano, Keiichi, Tabuchi, Norio
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US09/326,288
• Time in Patent Office: 750 Days
• Field of Search: 257/57, 257/59-60, 257/66, 257/72, 257/350, 349/42-44, 349/46
• US Class Current: 257/59
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A gate electrode (2), a gate insulating film (3), and an active layer (4) made of a poly silicon film and having a source (5), a channel (7), and a drain (6) are formed on an insulating substrate (1) and an interlayer insulating film (9) is formed over the whole of the gate insulating film (3), the active layer (4), and a stopper insulating film (8). A drain electrode (10) is formed by filling a contact hole made in the interlayer insulating film (9), the position of which corresponds to the drain (6), with a metal, such as Al. Simultaneously with the drain electrode (10), a conductive layer (11) is formed on the interlayer insulating film (9) over the channel (7). The conductive layer (11) is connected to gate signal line G on the insulating substrate (1) via a contact hole (15) made in the gate insulating film (3) and the interlayer insulating film (9). The width of the conductive layer (11) along the length of the channel (7) is narrower than the actual length of the channel (7) and narrower than the width along the channel length of the gate electrode (2). The conductive layer (11) can therefore shield the channel (7). As a result, even if impurities or the like become attached to the surface of the interlayer insulating film (9), the occurrence of a back channel, for example, is reliably prevented.

Claims

1. A thin film transistor, comprising:

an insulating substrate;

a gate electrode;

a gate insulating film;

a semiconductor film having a channel;

an interlayer insulating film; and

a planarization insulation film;

wherein the gate electrode, the gate insulating film, the semiconductor film having a channel, the interlayer insulating film, and the planarization insulation film are formed on the insulating substrate, wherein a conductive layer is formed opposite to the channel in the semiconductor film with, at least, the interlayer insulating film between, and wherein the width of the conductive layer along the length of the channel is narrower than the length of the channel, and the edge along the channel length of the conductive layer does not overlap with the edge along the channel length of the gate electrode or the edge along the channel length of the channel, and wherein the conductive layer is connected to the gate electrode.

2. The thin film transistor according to claim 1, wherein an insulating film including the interlayer insulating film is formed between the conductive layer and the semiconductor film and wherein the thickness of, at least, a region in the insulating film corresponding to the channel is 5,000 angstroms or more.

3. The thin film transistor according to claim 2, wherein the insulating film is made of a single layer of a silicon oxide film, a silicon nitride film, or a film made of an organic material, or is made of a laminate of any two or more of these films.

4. A display having the thin film transistor according to claim 1.

5. The thin film transistor according to claim 1, wherein the gate electrode, the gate insulating film, the semiconductor film, the interlayer insulating film, and the conductive layer are formed on an insulating substrate in that order or in a reverse order.

6. A thin film transistor, comprising:

an insulating substrate;

a gate electrode;

a gate insulating film;

a semiconductor film having a channel; and

an interlayer insulating film,

wherein the gate electrode, the gate film, the semiconductor film having a channel, and the interlayer insulating film are formed on the insulating substrate, wherein a conductive layer is formed opposite to the channel in the semiconductor film with, at least, the interlayer insulating film between, and wherein the width of the conductive layer along the length of the channel is narrower than the length of the channel and narrower than the width along the channel length of the gate electrode, and wherein the conductive layer is connected to the gate electrode.

7. The thin film transistor according to claim 6, wherein an insulating film including the interlayer insulating film is formed between the conductive layer and the semiconductor film and wherein the thickness of, at least, a region in the insulating film corresponding to the channel is 5,000 angstroms or more.

8. The thin film transistor according to claim 7, further comprising a planarization insulation film formed on the interlayer insulating film.

9. A display having the thin film transistor according to claim 6.

10. The thin film transistor according to claim 6, wherein the gate electrode, the gate insulating film, the semiconductor film, the interlayer insulating film, and the conductive layer are formed on an insulating substrate in that order or in a reverse order.

11. A thin film transistor, comprising:

an insulating substrate;

a gate signal line;

a data signal line; and

a thin film transistor near the intersection of the gate signal line and the data signal line,

wherein the gate signal line, the data signal line, and the thin film transistor near the intersection of the gate signal line and the data signal line are formed on the insulating substrate, the thin film transistor comprising;

a plurality of gate electrodes extending from or electrically connected to the gate signal line;

a gate insulating film;

a semiconductor film extending so as to overlap with the plurality of gate electrodes and having a channel in each of overlaps with the plurality of gate electrodes;

an interlayer insulating film;

a planarization insulation film; and

a conductive layer formed opposite to at least one of the channels with, at least, the interlayer insulating film between,

wherein the width along the channel length of the conductive layer is narrower than the length of the at least one channel overlapping with the conductive layer and than the width along the channel length of the corresponding gate electrode, and wherein the conductive layer is electrically connected to the gate signal line.

12. The semiconductor device according to claim 11, wherein an insulating film including the interlayer insulating film is formed between the conductive layer and the semiconductor film and wherein the thickness of, at least, a region in the insulating film corresponding to the channel is 5,000 angstroms or more.

13. A display having the thin film transistor according to claim 11.

14. The thin film transistor according to claim 11, wherein the plurality of a gate electrode, the gate insulating film, the semiconductor film, the interlayer insulating film, and the conductive layer are formed on an insulating substrate in that order or in a reverse order.

15. A thin film transistor, comprising:

an insulating substrate;

a gate electrode;

a gate insulating film;

a semiconductor film having a channel;

an interlayer insulating film; and

a planarization insulation film;

wherein the gate electrode, the gate insulating film, the semiconductor film having a channel, the interlayer insulating film, and the planarization insulation film are formed on the insulating substrate, wherein a conductive layer is formed opposite to the channel in the semiconductor film with, at least, the interlayer insulating film between, and wherein the width of the conductive layer along the length of the channel is narrower than the length of the channel, and the edge along the channel length of the conductive layer does not overlap with the edge along the channel length of the gate electrode or the edge along the channel length of the channel, and wherein the entire channel width is covered with the conductive layer, and wherein the conductive layer is connected to the gate electrode.

16. The thin film transistor according to claim 15, wherein an insulating film including the interlayer insulating film is formed between the conductive layer and the semiconductor film and wherein the thickness of, at least, a region in the insulating film corresponding to the channel is 5,000 angstroms or more.

17. The thin film transistor according to claim 16, wherein the insulating film is made of a single layer of a silicon oxide film, a silicon nitride film, or a film made of an organic material, or is made of a laminate of any two or more of these films.

18. A display having the thin film transistor according to claim 15.

19. The thin film transistor according to claim 15, wherein the gate electrode, the gate insulating film, the semiconductor film, the interlayer insulating film, and the conductive layer are formed on an insulating substrate in that order or in a reverse order.

20. A thin film transistor, comprising:

an insulating substrate;

a gate electrode;

a gate insulating film;

a semiconductor film having a channel; and

an interlayer insulating film,

wherein the gate electrode, the gate insulating film, the semiconductor film having a channel, and the interlayer insulating film are formed on the insulating substrate, wherein a conductive layer is formed opposite to the channel in the semiconductor film with, at least, the interlayer insulating film between, and wherein the width of the conductive layer along the length of the channel is narrower than the length of the channel and narrower than the width along the channel length of the gate electrode, and wherein the entire channel width is covered with the conductive layer, and wherein the conductive layer is connected to the gate electrode.

21. The thin film transistor according to claim 20, wherein an insulating film including the interlayer insulating film is formed between the conductive layer and the semiconductor film and wherein the thickness of, at least, a region in the insulating film corresponding to the channel is 5,000 angstroms or more.

22. The thin film transistor according to claim 21, further comprising a planarization insulation film formed on the interlayer insulating film.

23. A display having the thin film transistor according to claim 20.

24. The thin film transistor according to claim 20, wherein the gate electrode, the gate insulating film, the semiconductor film, the interlayer insulating film, and the conductive layer are formed on an insulating substrate in that order or in a reverse order.

25. A semiconductor device, comprising:

an insulating substrate;

a gate signal line;

a data signal line; and

a thin film transistor near the intersection of the gate signal line and the data signal line,

wherein the gate signal line, the data signal line, and the thin film transistor near the intersection of the gate signal line and the data signal line are formed on the insulating substrate, the thin film transistor comprising;

a plurality of hate electrodes extending from or electrically connected to the gate signal line;

a gate insulating film;

a semiconductor film extending so as to overlap with the plurality of gate electrodes and having a channel in each of overlaps with the plurality of gate electrodes;

an interlayer insulating film;

a planarization insulation film; and

a conductive layer formed opposite to at least one of the channels with, at least, the interlayer insulating film between,

wherein the width along the channel length of the conductive layer is narrower than the length of the at least one channel overlapping with the conductive layer and than the width along the channel length of the corresponding gate electrode, and wherein the entire channel width is covered with the conductive layer, and wherein the conductive layer is electrically connected to the gate signal line.

26. The semiconductor device according to claim 25, wherein an insulating film including the interlayer insulating film is formed between the conductive layer and the semiconductor film and wherein the thickness of, at least, a region in the insulating film corresponding to the channel is 5,000 angstroms or more.

27. A display having the thin film transistor according to claim 25.

28. The thin film transistor according to claim 25, wherein the plurality of a gate electrode, the gate insulating film, the semiconductor film, the interlayer insulating film, and the conductive layer are formed on an insulating substrate in that order or in a reverse order.