Embedded polysilicon gate MOSFET

• US 6,252,277 B1
• Filed: 09/09/1999
• Issued: 06/26/2001
• Est. Priority Date: 09/09/1999
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.), National University of Singapore
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.), National University of Singapore
• Inventors: Hao, Gong, Chan, Lap, Cha, Cher Liang, Chor, Eng Fong, Lee, Teck Koon
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/392,392
• Time in Patent Office: 656 Days
• Field of Search: 257/330, 257/332, 438/270, 438/276, 438/300
• US Class Current: 257/330
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

Formation of a MOSFET with a polysilicon gate electrode embedded within a silicon trench is described. The MOSFET retains all the features of conventional MOSFETs with photolithographically patterned polysilicon gate electrodes, including robust LDD (lightly doped drain) regions formed in along the walls of the trench. Because the gate dielectric is never exposed to plasma etching or aqueous chemical etching, gate dielectric films of under 100 Angstroms may be formed without defects. The problems of over etching, and substrate spiking which are encountered in the manufacture of photolithographically patterned polysilicon gate electrodes do not occur. The entire process utilizes only two photolithographic steps. The first step defines the silicon active area by patterning a field isolation and the second defines a trench within the active area wherein the device is formed. The new process, uses the same total number of photolithographic steps to form the MOSFET device elements as a conventional process but is far more protective of the thin gate oxide.

Claims

1. A method for forming and embedded polysilicon gate MOSFET comprising:

(a) providing a silicon wafer having an active region of a first conductivity type surrounded by a field isolation;

(b) depositing a doped oxide layer on said silicon wafer;

(c) forming an opening in said doped oxide layer, said opening bridging across said active region;

(d) forming silicon nitride spacers along the periphery of said opening;

(e) etching a trench in said opening;

(f) depositing a silicon oxide layer over said silicon wafer;

(g) planarizing said silicon oxide layer;

(h) etching said silicon oxide layer with a calibrated wet etch to expose the surface of said silicon wafer and said spacers while leaving a pocket of said silicon oxide layer in said trench, the surface of said pocket extending above the base of said spacers by a distance;

(i) selectively depositing an epitaxial silicon layer of a second conductivity type on said wafer, thereby forming source/drain regions;

(j) further etching said pocket to expose silicon along the sidewalls of said trench and leaving a residual portion of said pocket over the base of said trench;

(k) implanting ions of said second conductivity type into said sidewalls of said trench, thereby forming LDD regions;

(l) removing said residual portion;

(m) forming a gate oxide on the walls and base of said trench and a corresponding oxide layer on the surface of said source/drain regions;

(n) depositing a polysilicon layer over said wafer;

(o) planarizing said polysilicon layer;

(p) etching back said polysilicon layer, stopping in said corresponding oxide layer and leaving the level of the surface of said polysilicon in said trench between about 1,000 and 2,000 Angstroms above the base of said spacers, thereby forming an embedded gate electrode;

(q) removing said corresponding oxide layer, thereby exposing said source/drain regions; and

(r) forming a metal silicide on said source/drain regions and said polysilicon layer.

2. The method of claim 1 wherein said doped oxide layer is between about 1,000 and 3,000 Angstroms thick.

3. The method of claim 1 wherein said doped oxide layer is selected from the group consisting of a borophosphosilicate glass, and a phosphosilicate glass.

4. The method of claim 1 wherein said opening is rectangular across said bridging and wherein the channel length of said MOSFET is the width of said opening on said bridging as measured perpendicular to the direction of said bridging reduced by the widths of said spacers at their base.

5. The method of claim 1 wherein said spacers are between about 600 and 1,500 Angstroms wide at their base.

6. The method of claim 4 wherein the width of said trench as measured in the direction perpendicular to said bridging is between about 0.2 and 40 microns.

7. The method of claim 1 wherein said epitaxial layer is between about 1,000 and 1,500 Angstroms thick.

8. The method of claim 1 wherein said gate oxide is between about 30 and 200 Angstroms thick.

9. The method of claim 1 wherein said LDD elements extend beneath and under the base of said trench.

10. The method of claim 1 wherein said metal silicide is selected from the group consisting of titanium silicide, cobalt silicide, and nickel silicide.

11. The method of claim 1 wherein said polysilicon layer is of laminar construction having a first undoped portion which is in contact with said gate oxide and a second portion doped with an impurity.

12. The method of claim 1 wherein said distance is between about 100 and 400 Angstroms.

13. An embedded polysilicon gate MOSFET comprising:

(a) A silicon body of a first conductivity type with an active region bounded by a field isolation;

(b) a rectangular trench bridging across said active region, dividing said active region into two active surfaces, one on each side of said bridging;

(c) first regions of a second conductivity type comprising source/drain elements of said MOSFET, formed in said active surfaces and spaced laterally away from the mouth of said trench by a distance;

(d) second regions of said second conductivity type, formed on the sidewalls of said trench, contiguous with said first regions and extending vertically below the base of said trench, said second regions having a higher resistivity than said first regions and comprising LDD elements of said MOSFET;

(e) a gate oxide on the sidewalls and bottom of said trench; and

(f) a polysilicon body in said trench on said gate oxide comprising a gate electrode.

14. The MOSFET of claim 13 wherein said gate oxide is between about 30 and 200 Angstroms thick.

15. The MOSFET of claim 13 wherein said trench is between about 1,000 and 3,000 Angstroms deep.

16. The MOSFET claim 13 wherein said distance is between about 600 and 1,500 Angstroms.

17. The MOSFET of claim 13 wherein said polysilicon body is of laminar construction having a first undoped portion which is in contact with said gate oxide and a second portion doped with an impurity.

18. The method of claim 13 wherein said LDD elements extend beneath and under the base of said trench.

19. A method for forming and embedded polysilicon gate MOSFET comprising:

(a) providing a silicon wafer having an active region of a first conductivity type surrounded by a field isolation;

(b) depositing an oxide layer on said silicon wafer;

(c) forming an opening in said oxide layer, said opening bridging across said active region;

(d) forming silicon nitride spacers along the periphery of said opening;

(e) etching a trench in said opening;

(f) depositing a silicon oxide layer over said silicon wafer;

(g) anisotropically etching said silicon oxide layer to expose the surface of said silicon wafer and said spacers while leaving a pocket of said silicon oxide layer in said trench, said pocket extending upward to at least the base of said spacers;

(h) implanting ions of a second conductivity type into said wafer, thereby forming source/drain regions;

(i) further etching said pocket to expose silicon along the sidewalls of said trench and leaving a residual portion of said pocket over the base of said trench;

(j) implanting ions of said second conductivity type into said sidewalls of said trench, thereby forming LDD regions;

(k) removing said residual portion;

(l) forming a gate oxide on the walls and base of said trench and a corresponding oxide layer on the surface of said source/drain regions;

(m) depositing a polysilicon layer over said wafer;

(n) planarizing said polysilicon layer

(o) etching said polysilicon layer, stopping in said corresponding oxide layer and leaving the level of the surface of said polysilicon in said trench between about 1,000 and 2,000 Angstroms above the base of said spacers, thereby forming an embedded gate electrode;

(p) removing said corresponding oxide layer, thereby exposing said source/drain regions; and

(q) forming a metal silicide on said source/drain regions and on said polysilicon layer.

20. The method of claim 19 wherein said oxide layer is between about 1,000 and 3,000 Angstroms thick.

21. The method of claim 19 wherein said oxide layer is selected from the group consisting of silicon oxide, a borophosphosilicate glass, and a phosphosilicate glass.

22. The method of claim 19 wherein said opening is rectangular across said bridging and wherein the channel length of said MOSFET is the width of said opening on said bridging as measured perpendicular to the direction of said bridging reduced by the widths of said spacers at their base.

23. The method of claim 19 wherein said spacers are between about 600 and 1,500 Angstroms wide at their base.

24. The method of claim 22 wherein the width of said trench as measured in the direction perpendicular to said bridging is between about 0.2 and 40 microns.

25. The method of claim 19 wherein said gate oxide is between about 30 and 200 Angstroms thick.

26. The method of claim 19 wherein said LDD elements extend beneath and under the base of said trench.

27. The method of claim 19 wherein said metal silicide is selected from the group consisting of titanium silicide, cobalt sulicide, and nickel silicide.

28. The method of claim 19 wherein said polysilicon layer is of laminar construction having a first undoped portion which is in contact with said gate oxide and a second portion doped with an impurity.