Laser antifuse using gate capacitor

• US 6,252,293 B1
• Filed: 07/02/1998
• Issued: 06/26/2001
• Est. Priority Date: 01/04/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ma, Manny K. F., Seyyedy, Mirmajid
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US09/109,605
• Time in Patent Office: 1,090 Days
• Field of Search: 257/530, 257/209, 257/410
• US Class Current: 257/530
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 23/5254 the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit laser antifuse is described which has two physical states. In the first physical state the laser antifuse has to conductive plates electrically separated by a layer of dielectric material. In the second physical state the two conductive plates are electrically connected through the dielectric in response to an external radiation source, such as a laser.

Claims

1. An integrated circuit laser antifuse having first and second states, comprising:

a first conductive plate;

a second conductive plate, wherein the second conductive plate comprises an active area of an integrated circuit;

a layer of dielectric material located between the first conductive plate and the second conductive plate; and

at least two circuit connection regions extending into the second conductive plate and electrically connected to the second conductive plate, wherein the at least two circuit connection regions are physically separated from each other;

wherein the first conductive plate and the at least circuit connection regions are electrically isolated in the first state, and wherein the first conductive plate and the at least two circuit connection regions are electrically connected in the second state upon electrically connecting the first conductive plate and the second conductive plate through the layer of dielectric material in response to a focused external radiation source.

2. The integrated circuit laser antifuse of claim 1 wherein the first conductive plate comprises a layer of polysilicon fabricated on the layer of dielectric material.

3. The integrated circuit laser antifuse of claim 1 wherein the dielectric material comprises material selected from the group consisting of oxide and barium strontium titanium.

4. The integrated circuit laser antifuse of claim 1 wherein the second conductive plate comprises an N-well fabricated in a P-substrate.

5. The integrated circuit laser antifuse of claim 4 wherein the at least two circuit connection regions comprise N+ contact regions fabricated in the N-well.

6. The integrated circuit laser antifuse of claim 1 wherein the second conductive plate comprises a P-well fabricated in an N-substrate.

7. The integrated circuit laser antifuse of claim 6 wherein the at least two circuit connection regions comprise P+ contact regions fabricated in the P-well.

8. The integrated circuit laser antifuse of claim 1 wherein the focused external radiation source comprises a laser.

9. A method of programming an integrated circuit laser antifuse having first and second states, wherein the integrated circuit laser antifuse comprises a first conductive plate, a second conductive plate comprising an active area of an integrated circuit, a layer of dielectric material located between the first conductive plate and the second conductive plate and electrically isolating the first conductive plate from the second conductive plate in the first state, and at least two circuit connection regions extending into the second conductive plate and electrically connected to the second conductive plate, wherein the at least two circuit connection regions are physically separated from each other, the method comprising:

focusing an external radiation source on the first conductive plate while in the first state; and

forming a conductive path from the first conductive plate through the layer of dielectric material to the second conductive plate, thereby producing the second state and electrically connecting each of the at least two circuit connection regions to the first conductive plate.

10. The method of claim 9 wherein focusing an external radiation source comprises focusing a laser.

11. A method of programming an integrated circuit laser antifuse having first and second states, wherein the integrated circuit laser antifuse comprises a first conductive plate, a second conductive plate comprising an active area of an integrated circuit, a layer of barium strontium titanium located between the first conductive plate and the second conductive plate and electrically isolating the first conductive plate from the second conductive plate in the first state, and at least two circuit connection regions extending into the second conductive plate and electrically connected to the second conductive plate, wherein the at least two circuit connection regions are physically separated from each other, the method comprising:

focusing a laser on the first conductive plate while in the first state; and

forming a conductive path from the first conductive plate through the layer of barium strontium titanium to the second conductive plate, thereby producing the second state and electrically connecting each of the at least two circuit connection regions to the first conductive plate.

12. An integrated circuit, comprising:

an integrated circuit laser antifuse having first and second states, wherein the integrated circuit laser antifuse comprises;

a first conductive plate;

a second conductive plate, wherein the second conductive plate comprises an active area of an integrated circuit;

a layer of dielectric material located between the first conductive plate and the second conductive plate; and

at least two circuit connection regions extending into the second conductive plate and electrically connected to the second conductive plate, wherein the at least two circuit connection regions are physically separated from each other;

wherein the first conductive plate and the at least two circuit connection regions are electrically isolated in the first state, and wherein the first conductive plate and the at least two circuit connection regions are electrically connected in the second state upon electrically connecting the first conductive plate and the second conductive plate through the layer of dielectric material in response to a focused external radiation source.

13. The integrated circuit of claim 12 wherein the first conductive plate comprises a layer of polysilicon fabricated on the layer of dielectric material.

14. The integrated circuit of claim 12 wherein the dielectric material comprises material selected from the group consisting of oxide and barium strontium titanium.

15. The integrated circuit of claim 12 wherein the second conductive plate comprises an N-well fabricated in a P-substrate.

16. The integrated circuit of claim 15 wherein the at least two circuit connection regions comprise N+ contact regions fabricated in the N-well.

17. The integrated circuit of claim 12 wherein the second conductive plate comprises a P-well fabricated in an N-substrate.

18. The integrated circuit of claim 17 wherein the at least two circuit connection regions comprise P+ contact regions fabricated in the P-well.

19. The integrated circuit of claim 12 wherein the focused external radiation source comprises a laser.

20. An integrated circuit memory device, comprising:

a memory array;

a column address decoder circuit coupled to the memory array;

a row address decoder circuit coupled to the memory array; and

at least one integrated circuit laser antifuse having first and second states, wherein each at least one integrated circuit laser antifuse is coupled to a circuit selected from the group consisting of the column address decoder circuit and the row address decoder circuit, further wherein each at least one integrated circuit laser antifuse comprises;

a first conductive plate;

a second conductive plate, wherein the second conductive plate comprises an active area of an integrated circuit;

a layer of dielectric material located between the first conductive plate and the second conductive plate; and

at least two circuit connection regions extending into the second conductive plate and electrically connected to the second conductive plate, wherein the at least two circuit connection regions are physically separated from each other;

wherein the first conductive plate and the at least two circuit connection regions are electrically isolated in the first state, and wherein the first conductive plate and the at least two circuit connection regions are electrically connected in the second state upon electrically connecting the first conductive plate and the second conductive plate through the layer of dielectric material in response to a focused external radiation source.

21. The integrated circuit memory device of claim 20 wherein the first conductive plate comprises a layer of polysilicon fabricated on the layer of dielectric material.

22. The integrated circuit memory device of claim 20 wherein the dielectric material comprises material selected from the group consisting of oxide and barium strontium titanium.

23. The integrated circuit memory device of claim 20 wherein the second conductive plate comprises an N-well fabricated in a P-substrate.

24. The integrated circuit memory device of claim 23 wherein the at least two circuit connection regions comprise N+ contact regions fabricated in the N-well.

25. The integrated circuit memory device of claim 20 wherein the second conductive plate comprises a P-well fabricated in an N-substrate.

26. The integrated circuit memory device of claim 25 wherein the at least two circuit connection regions comprise P+ contact regions fabricated in the P-well.

27. The integrated circuit memory device of claim 20 wherein the focused external radiation source comprises a laser.

28. An integrated circuit programmable memory device, comprising:

a word line;

a digit line;

a plurality of access transistors, wherein each one of the plurality of access transistors comprises a first source/drain coupled to the digit line, a gate coupled to the word line and a second source/drain; and

a plurality of laser antifuse memory cells, wherein each one of the plurality of laser antifuse memory cells has first and second states, further wherein each one of the plurality of laser antifuse memory cells is coupled to the second source/drain, still further wherein each one of the plurality of laser antifuse memory cells comprises;

a first conductive plate;

a second conductive plate, wherein the second conductive plate comprises an active area of an integrated circuit;

a layer of dielectric material located between the first conductive plate and the second conductive plate; and

at least two circuit connection regions extending into the second conductive plate and electrically connected to the second conductive plate, wherein the at least two circuit connection regions are physically separated from each other;

wherein the first conductive plate and the at least two circuit connection regions are electrically isolated in the first state, and wherein the first conductive plate and the at least two circuit connection regions are electrically connected in the second state upon electrically connecting the first conductive plate and the second conductive plate through the layer of dielectric material in response to a focused external radiation source.

29. The integrated circuit programmable memory device of claim 28 wherein the first conductive plate comprises a layer of polysilicon fabricated on the layer of dielectric material.

30. The integrated circuit programmable memory device of claim 28 wherein the dielectric material comprises material selected from the group consisting of oxide and barium strontium titanium.

31. The integrated circuit programmable memory device of claim 28 wherein the second conductive plate comprises an N-well fabricated in a P-substrate.

32. The integrated circuit programmable memory device of claim 31 wherein the at least two circuit connection region comprise N+ contact regions fabricated in the N-well.

33. The integrated circuit programmable memory device of claim 28 wherein the second conductive plate comprises a P-well fabricated in an N-substrate.

34. The integrated circuit programmable memory device of claim 33 wherein the at least two circuit connection regions comprise P+ contact regions fabricated in the P-well.

35. The integrated circuit programmable memory device of claim 28 wherein the focused external radiation source comprises a laser.