Apparatus for rapidly charging and reconditioning a battery

• US 6,252,373 B1
• Filed: 08/30/2000
• Issued: 06/26/2001
• Est. Priority Date: 04/26/1999
• Status: Expired due to Fees

• Current Assignee: ION Control Solutions
• Original Assignee: ION Control Solutions
• Inventors: Stefansson, Hafthor, Tiso, Michael
• Primary Examiner(s): Tso, Edward H.
• Application Number:
  US09/650,889
• Time in Patent Office: 300 Days
• Field of Search: 320/106, 320/110, 320/118, 320/127, 320/128, 320/124, 320/125, 320/132, 320/139, 320/141, 320/160
• US Class Current: 320/106
• CPC Class Codes: H02J 7/00711 with introduction of pulses during the charging process

Abstract

Apparatus for rapidly charging a battery including an output adapted to be electrically connected to a battery and a control device electrically connected to the output. The control device includes a power supply and a microcontroller. The microcontroller includes PWM firmware using software interleaving for controlling the power supply and a plurality of battery charging stages.

Claims

1. An apparatus for rapidly charging a battery comprising:

an output adapted to be electrically connected to a battery; and

a control device electrically connected to said output, said control device including a power supply and a microcontroller, said microcontroller including software for controlling said power supply and selecting and sequencing a plurality of software defined battery charging profiles to control the output of said power supply to the battery.

2. The apparatus of claim 1, wherein said control device further comprising:

a charge pulse generator adapted to provide a charge pulse at said output to charge the battery;

a discharge device adapted to provide a discharge pulse at said output to drain current from the battery to lower the impedance of the battery, with a predetermined ratio of the duration of the charge pulse to the discharge pulse; and

a control device alternatively connecting said discharge device, and said charge pulse generator to said output so as to alternatingly provide said discharge pulse, and said charge pulse, and an electrically neutral rest period, respectively, to the battery, said discharge pulse, charge pulse, and rest period being applied to the battery in a predetermined charging sequence controlled by said microcontroller through said software, said discharge pulse is applied substantially immediately prior to said charge pulse in said predetermined charging sequence.

3. A method of rapidly charging a battery by a battery charger having a microcontroller with firmware and an input connected to a source of power, the battery charger providing charge pulses to the battery, the charging method comprising the steps of:

a) running an initialization process for the battery charger;

b) determining the type and rating of the battery to be charged;

c) selecting an initial charging profile based on the battery information;

d) running the initial battery charging stage;

e) determining by comparing with predetermined time factors, whether voltage level of the battery has ramped up too rapidly or too slowly, and terminating charging process accordingly to protect the battery from being damaged;

f) monitoring the condition of the battery; and

g) selecting and running another battery charging stage upon sensing a predefined battery condition limit.

4. The method of claim 3, wherein the step of running an initialization process further comprises the step of determining whether a battery has been connected to the charger.

5. The method of claim 4, wherein said determining step further comprises the step of determining whether a battery has been connected to the charger further comprises the step of determining whether the voltage of the power supply is at its maximum but without current flow.

6. The method of claim 3, wherein said determining step (e) further comprises the step of sensing of a minimum rest voltage of the battery and selecting a charging sequence accordingly.

7. The method of claim 3, wherein said selecting step (c) further comprises the step of comparing the information acquired by said determining step (e) and matching said battery condition with an optimal charging profile.

8. The method of claim 7, wherein said charging profile comprises a plurality of charging stages including:

a) a battery wake up stage;

b) a bulk charge stage;

c) an equalizing charge stage; and

d) a constant holding voltage stage.

9. The method of claim 3, wherein said determining step (e) further comprises the step of taking at least two voltage measurements of the battery during at least one predetermined time interval.

10. The method of claim 3, wherein the step of monitoring the condition of the battery further comprises the step of sensing, at predetermined time intervals, the level of charge of the battery including taking measurements of the battery voltage and the clock time during the entire charging process.

11. The method of claim 3, wherein said selecting step (g) further comprises the step of comparing the monitored battery condition with a table of predefined battery condition patterns and stages and selecting a battery charging stage corresponding to a battery condition pattern which most closely matches the monitored battery condition.

12. A method of regulating the total output of power supply using a microcontroller with predefined instructions, the regulating method comprising the steps of:

a) producing a pulse width modulation waveform based on the predefined instructions to control the power supply; and

b) interleaving the pulse width modulation waveform to simulate increased resolution of the power supply.

13. The method of claim 12, wherein the step of producing a pulse width modulation waveform to control the power supply further comprises the steps of:

a) dividing pulse width modulation state variables by a predetermined value, to set on-time, and storing the remainder;

b) incrementing an internal wave counter;

c) checking whether wave counter is larger than the predetermined value, and if larger, setting wave counter to zero;

d) determining the relationship between said remainder and wave counter and incrementing on-time by a predetermined amount;

e) checking whether off-time is at maximum, and if maximum, turning pulse width modulation on;

f) checking whether on-time is at minimum, and if minimum, turning pulse width modulation off;

g) setting off-time equal to total wave time minus on-time;

h) decrementing both on and off times by an amount corresponding to the time the charger takes to actually turn on and off the pulse width modulation;

i) checking whether on-time is more than off-time, and if true, turning off pulse width modulation; and

j) checking whether on-time is more than off-time, and if untrue, turning on pulse width modulation.

14. The method of claim 13, wherein said checking step (e) further comprises the step of idling for the remaining time which is equivalent of total time minus pulse width modulation turn on-time.

15. The method of claim 13, wherein said checking step (f) further comprises the step of idling for the remaining time which is equivalent to total time equal minus pulse width modulation turn off-time.

16. The method of claim 12, further comprising the steps of:

a) loading the battery in a load flow stage;

b) resting pre-pulse in a rest flow stage;

c) pulsing in a pulse flow stage;

d) resting post-pulse in rest flow stage;

e) checking timer whether time limit reached; and

f) repeating steps a) through e) if within time limit.

17. The method of claim 16, further comprising the steps of:

a) checking whether a load has been detected;

b) applying a load;

c) waiting for load-time; and

d) checking whether time limit reached.

18. The method of claim 16, further comprising the steps of:

a) checking whether the charger is in rest stage;

b) waiting for rest time; and

c) checking whether time limit has reached.

19. The method of claim 12, wherein said interleaving step further comprises the steps of:

a) disabling interrupts;

b) selecting current channel; and

c) selecting voltage channel.

20. The method of claim 19, wherein the step of selecting current channel further comprises the steps of:

a) setting a read counter;

b) producing a pulse width modulation waveform to control the power supply;

c) sensing current;

d) adding the sensed current to a current tally;

e) decrementing the read counter;

f) checking whether the read counter reached zero;

g) returning to step b) if the read counter is not zero, dividing the current tally by original read counter;

h) checking whether a pulse is complete; and

i) if complete, reenabling interrupts.

21. The method of claim 19, wherein the step of selecting voltage channel further comprising the steps of:

a) setting a read counter;

b) producing a pulse width modulation waveform to control the power supply;

c) sensing voltage;

d) adding the sensed voltage to a voltage tally;

e) decrementing the read counter;

f) checking whether the read counter reached zero;

g) returning to step b) if the read counter is not zero, dividing the voltage tally by original voltage read counter;

h) checking whether a pulse is complete; and

i) if complete, reenabling interrupts.

22. A method of obtaining high resolution readings of an output of a power supply, the method comprising the steps of:

a) generating a pulse width modulation waveform using software interleaving;

b) taking an A/D measurement of the output of the power supply;

c) adding said A/D measurement to an accumulator;

d) repeating steps a) through c) until a predetermined number of measurements are taken; and

e) dividing the accumulator total by the specified number of measurements to obtain a high resolution reading.

23. A machine-readable program storage device for storing encoded instructions for a method of regulating the total output of power supply using a microcontroller, the regulating method comprising the steps of:

a) producing a pulse width modulation waveform according to a predetermined series of stages to control the power supply;

b) interleaving the pulse width modulation waveform to simulate increased resolution of the power supply.

24. The machine-readable program storage device of claim 23, wherein said step of producing a pulse width modulation waveform to control the power supply further comprises the steps of:

a) dividing pulse width modulation state variables by a predetermined value to set on-time and storing the remainder microseconds;

b) incrementing internal wave counter;

c) checking whether wave counter is larger than the predetermined value, and if larger, setting wave counter to zero;

d) determining the relationship between said remainder and wave counter and incrementing on-time by a predetermined amount accordingly;

e) checking whether off-time is at maximum, and if maximum, turning pulse width modulation on;

f) checking whether on-time is at minimum, and if minimum, turning pulse width modulation off;

g) setting off-time equal to total wave time minus on-time;

h) decrementing both on and off times by an amount corresponding to the time the charger takes to actually turn on and off the pulse width modulation;

i) checking whether on-time is more than off-time, and if true, turning off pulse width modulation; and

j) checking whether on-time is more than off-time, and if untrue, turning on pulse width modulation.

25. The machine-readable program storage device of claim 24, wherein said checking step (e) further comprises the step of idling for the remaining time which is equivalent of total time minus pulse width modulation turn on-time.

26. The machine-readable program storage device of claim 24, wherein said checking step (f) further comprising the steps of idling for the remaining time which is equivalent to total time equal minus pulse width modulation turn off time.

27. The machine-readable program storage device of claim 23, further comprising the steps of:

a) loading the battery in a load flow stage;

b) resting pre-pulse in a rest flow stage;

c) pulsing in a pulse flow stage;

d) resting post-pulse in rest flow stage;

e) checking timer whether time limit reached; and

f) repeating steps a) through e) if within time limit.

28. The machine-readable program storage device of claim 27 further comprising the steps of:

a) checking whether a load has been detected;

b) applying a load;

c) waiting for load-time; and

d) checking whether time limit reached.

29. The machine-readable program storage device of claim 27, wherein the step of running the firmware in a rest flow stage further comprising the steps of:

a) checking whether the charger is in rest stage;

b) waiting for rest time; and

c) checking whether time limit has reached.

30. The machine-readable program storage device of claim 23, wherein the step of using a software interleave of the pulse width modulation waveform to simulate increased resolution of the power supply further comprising the steps of:

a) disabling interrupts;

b) selecting current channel; and

c) selecting voltage channel.

31. The machine-readable program storage device of claim 30, wherein the step of selecting current channel further comprises the steps of:

a) setting a read counter;

b) producing a pulse width modulation waveform to control the power supply;

c) sensing current;

d) adding the sensed current to a current tally;

e) decrementing the read counter;

f) checking whether the read counter reached zero; and

g) returning to step b) if the read counter is not zero;

h) checking whether a pulse is completed; and

i) reenabling interrupts.

32. The machine-readable program storage device of claim 30, wherein the step of selecting voltage channel further comprising the steps of:

a) setting a read counter;

b) producing a pulse width modulation waveform to control the power supply;

c) sensing voltage;

d) adding the sensed voltage to a voltage tally;

e) decrementing the read counter;

f) checking whether reading counter reached zero;

g) returning to step b) if the read counter is not zero, and dividing the voltage tally by the original voltage read counter;

h) checking whether a pulse is complete; and

i) if complete, reenabling interrupts.