Power management system and current augmentation and battery charger method and apparatus for a computer peripheral

• US 6,252,375 B1
• Filed: 07/25/2000
• Issued: 06/26/2001
• Est. Priority Date: 07/24/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: In-System Design Incorporated (Infineon Technologies AG)
• Inventors: Richter, Ronald J., DeHart, Scott A.
• Primary Examiner(s): Tso, Edward H.
• Application Number:
  US09/626,368
• Time in Patent Office: 336 Days
• Field of Search: 320/127, 320/124, 320/135, 320/137, 320/157, 320/160, 320/163
• US Class Current: 320/127
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: H02J 1/10 Parallel operation of dc sources
• CPC Class Codes: H02J 7/0068 Battery or charger load switching, e.g. concurrent charging and load supply H02J7/0013 takes precedence

Abstract

The current augmentation method is for use with a computer powered peripheral subsystem including a dynamic load, the dynamic load requiring greater power, from time to time, than the specified power available from the computer and specified interconnect bus or interface. This method includes use of a power node supplying power as necessary from the battery to the dynamic load, such that the varying dynamic load does not exceed the specified power available from the computer and interconnect bus. The method includes monitoring the load current, and injecting current into the power node to augment the current drive capability of the computer and peripheral bus. Preferably, the injecting is performed selectively based upon the result of the monitoring, e.g. only when the sensed load current is approaching a defined threshold level. Further, battery charging is performed only when it is determined that no current is being drawn through the battery to avoid distorting the voltage reading. The invented apparatus is also for selectively charging the battery from the current on the bus during relatively idle periods of peripheral dynamic load. The apparatus includes means for determining the chargeability of the battery in accordance with predefined chargeability criteria, and a battery charging circuit responsive to the determining means for selectively charging the battery only during times when the peripheral load current is limited and there is sufficient current available on the bus from the computer to recharge the battery.

Claims

1. For use with a battery-powered computer interface including a dynamic load powered by a power node connected with a battery having a characteristic drive capability, a current augmentation method comprising:

monitoring the dynamic load on the computer interface by one or more of load voltage sensing and load current sensing, and

injecting current into the power node to augment the current drive capability of the interface.

2. The method of claim 1 wherein said injecting is performed selectively based upon the result of said monitoring.

3. The method of claim 2 wherein said injecting is performed only when the sensed load voltage is less than a defined threshold level.

4. The method of claim 2 wherein said injecting is performed only when the sensed load current is less than a defined threshold level.

5. The method of claim 2, which further comprises charging the battery, wherein said charging is performed only when it is determined that substantially no current is being drawn through the battery.

6. Apparatus for selectively charging a battery from a voltage source on a bus during periods of relative idle of a bus-connected load, the apparatus comprising:

means for determining the chargeability of the battery in accordance with predefined chargeability criteria, and

a battery charging circuit responsive to said determining means for selectively charging the battery only during times of relative battery chargeability.

7. The apparatus of claim 6 wherein said determining means includes a surplus current detector operative to detect when the dynamic load is drawing sufficiently less than a defined current to permit battery charging.

8. The apparatus of claim 6 wherein said battery charge circuit charges the battery by injecting a pulsed charge current into the battery, the pulsed charge current defining an on time when current is injected and an off time when current is not injected, and wherein said determining means includes a battery voltage detector operative to measure the voltage level of the battery when said pulsed charge current is off.

9. The apparatus of claim 6 wherein said determining means includes a load voltage sensing mechanism operative to periodically sense the load voltage and wherein said determining means further includes a comparison means for comparing the sensed load voltage with predefined load voltage criteria.

10. The apparatus of claim 6 wherein said determining means includes a load current sensing mechanism operative to periodically sense the load current and wherein said determining means further includes comparison means for comparing the sensed load current with predefined load current criteria.

11. The apparatus of claim 6 wherein said determining means includes a load voltage sensing mechanism operative to periodically sense the load voltage and wherein said determining means further includes a comparison means for comparing the sensed load voltage with predefined load voltage criteria and wherein said determining means further includes a load current sensing mechanism operative to periodically sense the load current and wherein said determining means further includes a comparison means for comparing the sensed load current with predefined load current criteria.

12. A power management system for a peripheral connected with a computer providing a voltage source on a bus, the system comprising:

a battery;

a processor;

a memory containing instructions executable by said processor;

a first analogue-to-digital converter (ADC) coupled with said processor for digitizing a battery voltage;

a battery voltage sensing circuit connected to said battery for sensing the voltage output by the battery and providing the sensed voltage to said ADC;

a battery charging circuit connected with the voltage source on the bus for selectively charging said battery responsive to a command from said processor; and

a current augmentation circuit connected with said one or more ADCs and said battery charging circuit for injecting current into a power node of the computer peripheral responsive to a command from said processor.

13. The system of claim 12 which comprises a second ADC coupled with said processor for digitizing a peripheral load current, wherein both the battery voltage and the peripheral load current are digitized and wherein said processor monitors the same to selectively generate said commands to said battery charging circuit and said current augmentation circuit based at least in part upon both the battery voltage and the peripheral load current.

14. The system of claim 12 which is integrally housed within the peripheral.

15. The system of claim 12 which is integrally housed within an interface cable configured to extend between the computer and the peripheral.