Overvoltage-tolerant interface for intergrated circuits

• US 6,252,422 B1
• Filed: 09/22/1999
• Issued: 06/26/2001
• Est. Priority Date: 05/28/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wong, Wilson, Patel, Rakesh H., Turner, John E.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): PAIK, STEVEN SANGYUL
• Application Number:
  US09/400,953
• Time in Patent Office: 643 Days
• Field of Search: 326/68, 326/80-81, 326/83, 326/86, 326/121
• US Class Current: 326/80
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018585 programmable

Abstract

An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.

Claims

1. A high-voltage-tolerant interface circuit for an integrated circuit comprising:

a first pull-up device coupled between a first supply voltage and an I/O pad;

a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device; and

a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third pull-up device,

wherein the third control electrode of the third pull-up device is coupled through a path which comprises no active devices to the fir t control electrode of the first pull-up device.

2. The high-voltage-tolerant interface circuit of claim 1 further comprising:

a first pull-down device coupled between the output pad and a third supply voltage; and

a second pull-down device coupled between the first control electrode of the first pull-up device and the third supply voltage.

3. The high-voltage-tolerant interface circuit of claim 2 wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices.

4. The high-voltage-tolerant interface circuit of claim 2 further comprising:

a first pass device coupled between first node and the second control electrode of the second pull up device, wherein a control electrode of the first pass device is coupled to the first supply voltage,

wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices, and a gate oxide thickness of the thick oxide device is greater than a gate oxide thickness of the first pass device.

5. A high-voltage-tolerant interface circuit for an integrated circuit comprising:

a first pull-up device coupled between a first supply voltage and an I/O pad;

a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device; and

a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third pull-up device,

wherein a path between the third control electrode of the third pull-up device and the first control electrode of the first pull-up device has no transistors.

6. The high-voltage-tolerant interface circuit of claim 5 further comprising:

a first pull-down device coupled between the output pad and a third supply voltage; and

a second pull-down device coupled between the first control electrode of the first pull-up device and the third supply voltage.

7. The high-voltage-tolerant interface circuit of claim 6 wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices.

8. The high-voltage-tolerant interface circuit of claim 6 further comprising:

a first pass device coupled between a first node and the second control electrode of the second pull up device, wherein a control electrode of the first pass device is coupled to the first supply voltage,

wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second mull-down device are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the first pass device.

9. A high-voltage-tolerant interface circuit for an integrated circuit comprising:

a first pull-up device coupled between a first supply voltage and an I/O pad;

a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device; and

a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third pull-up device,

wherein the third control electrode of the third pull-up device is directly coupled to the first control electrode of the first pull-up device.

10. The high-voltage-tolerant interface circuit of claim 9 further comprising:

a first pull-down device coupled between the output pad and a third supply voltage; and

a second pull-down device coupled between the first control electrode of the first pull-up device and the third supply voltage.

11. The high-voltage-tolerant interface circuit of claim 10 wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices.

12. The high-voltage-tolerant interface circuit of claim 10 further comprising:

a first pass device coupled between a first node and the second control electrode of the second pull up device, wherein a control electrode of the first pass device is coupled to the first supply voltage,

wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the first pass device.

13. A high-voltage-tolerant interface circuit for an integrated circuit comprising:

a first pull-up device coupled between a first supply voltage and an I/O pad;

a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device; and

a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third pull-up device,

wherein the third control electrode of the third pull-up device is coupled through a path comprising no signal inversions to the first of control electrode of the first pull-up device.

14. The high-voltage-tolerant interface circuit of claim 13 further comprising:

a first pull-down device coupled be ween the output pad and a third supply voltage; and

a second pull-down device coupled between the first control electrode of the first pull-up device and the third supply voltage.

15. The high-voltage-tolerant interface circuit of claim 14 wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices.

16. The high-voltage-tolerant interface circuit of claim 14 further comprising:

a first pass device coupled between first node and the second control electrode of the second pull up device, wherein a control electrode of the first pass device is coupled to the first supply voltage,

wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second p all-down device are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the first pass device.

17. A high-voltage-tolerant interface circuit for an integrated circuit comprising:

a first pull-up device coupled between a first supply voltage and an I/O pad;

a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device; and

a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, where in a third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third full-up device,

wherein a signal provided at the first control electrode of the first pull-up device is solely dependent on a signal provided at the third control electrode of the third pull-up device.

18. The high-voltage-tolerant interface circuit of claim 17 further comprising:

a first pull-down device coupled between the output pad and a third supply voltage; and

a second pull-down device coupled between the first control electrode of the first pull-up device and the third supply voltage.

19. The high-voltage-tolerant interface circuit of claim 18 wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices.

20. The high-voltage-tolerant interface circuit of claim 18 further comprising:

a first pass device coupled between a first node and the second control electrode of the second pull up device, wherein a control electrode of the first pass device is coupled to the first supply voltage,

wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the first pass device.

21. A high-voltage-tolerant interface circuit for an inte-grated circuit comprising:

a first pull-up device coupled between a first supply voltage and an I/O pad;

a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device; and

a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third pull-up device,

wherein a signal transition provide at the first control electrode of the first pull-up device is dependent only on a signal transit on at the third control electrode of the third pull-up device.

22. The high-voltage-tolerant interface circuit of claim 21 further comprising:

a first pull-down device coupled between the output pad and a third supply voltage; and

a second pull-down device coupled between the first control electrode of the first pull-up device and the third supply voltage.

23. The high-voltage-tolerant interface circuit of claim 22 wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices.

24. The high-voltage-tolerant interface circuit of claim 22 further comprising:

a first pass device coupled between a first node and the second control electrode of the second pull up device, wherein a control electrode of the first pass device is coupled to the first supply voltage,

wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the first pass device.

25. A high-voltage-tolerant interface circuit for an integrated circuit comprising:

a first pull-up device coupled between a first supply voltage and an I/O pad;

a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device; and

a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third pull-up device,

wherein a logic signal transition at th first control electrode of the first pull-up device is logically dependent only on a logic signal transition at the third control electrode of the third pull-up device.

26. The high-voltage-tolerant interface circuit of claim 25 further comprising:

a first pull-down device coupled between the output pad and a third supply voltage; and

a second pull-down device coupled between the first control electrode of the first pull-up device and the third supply voltage.

27. The high-voltage-tolerant interface circuit of claim 26 wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices.

28. The high-voltage-tolerant interface circuit of claim 26 further comprising:

a first pass device coupled between first node and the second control electrode of the second pull up device, wherein a control electrode of the first pass device is coupled to the first supply voltage,

wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices, and a gate oxide thickness of the thick oxide device is greater than a gate oxide thickness of the first pass device.

29. A high-voltage-tolerant interface circuit for an integrated circuit comprising:

a first pull-up device coupled between a first supply voltage and an I/O pad;

a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device;

a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third pull-up device;

a first pull-down device coupled be ween the first control electrode of the first pull-up device and a third supply voltage;

a second pull-down device coupled between the output pad and the third supply voltage; and

a first pass device coupled between first node and the second control electrode of the second pull up device, wherein a control electrode of the first pass device is coupled to the first supply voltage.

30. The high-voltage-tolerant interface circuit of claim 29 further comprising:

a first inverter coupled between the control electrode of the first pull-down device and a second node; and

a second inverter coupled between the second node and the first node.

31. The high-voltage-tolerant interface circuit of claim 29 wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the first pass device.

32. A programmable logic integrated circuit comprising:

a plurality of logic array blocks;

a plurality of programmable interconnect, programmably coupled to the plurality of logic array blocks; and

at least one high-voltage-tolerant interface circuit block, programmably coupled to the programmable interconnect, comprising;

a first pull-up device coupled between a first supply voltage and an I/O pad;

a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device; and

a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third pull-up device,

wherein a signal transition provided at the first control electrode of the first pull-up device is dependent only on a signal transition at the third control electrode of the third pull-up device.

33. The programmable logic integrated circuit of claim 32 wherein the at least one high-voltage-tolerant interface circuit block further comprises:

a first pull-down device coupled between the output pad and a third supply voltage; and

a second pull-down device coupled between the first control electrode of the first pull-up device and the third supply voltage.

34. The programmable logic integrated circuit of claim 33 wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices.

35. The programmable logic integrated circuit of claim 33 wherein the at least one high-voltage-tolerant interface circuit block further comprises:

a first pass device coupled between a first node and the second control electrode of the second pull up device, wherein a control electrode of the first pass device is coupled to the first supply voltage,

wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the first pass device.

36. A programmable logic integrated circuit comprising:

a plurality of logic array blocks;

a plurality of programmable interconnect, programmably coupled to the plurality of logic array blocks; and

at least one high-voltage-tolerant interface circuit block, programmably coupled to the programmable interconnect, comprising;

a first pull-up device couple between a first supply voltage and an I/O pad;

a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device; and

a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device wherein a third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third pull-up device,

wherein a logic signal transition at the first control electrode of the first pull-up device is logically dependent only on a logic signal transition at the third control electrode of the third pull-up device.

37. The programmable logic integrated circuit of claim 36 wherein the at least one high-voltage-tolerant interface circuit block further comprises:

a first pull-down device coupled between the output pad and a third supply voltage; and

a second pull-down device coupled between the first control electrode of the first pull-up device and the third supply voltage.

38. The programmable logic integrated circuit of claim 37 wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices.

39. The programmable logic integrated circuit of claim 37 wherein the at least one high-voltage-tolerant interface circuit block further comprises:

a first pass device coupled between a first node and the second control electrode of the second pull up device, wherein a control electrode of the first pass device is coupled to the first supply voltage,

wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the first pass device.

40. A high-voltage-tolerant interface circuit for an integrated circuit comprising:

a first transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to an I/O pad and the source is coupled to a first supply voltage;

a second transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the first transistor and the source is coupled to a second supply voltage; and

a third transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the second transistor, the source is coupled to the second supply, the gate is coupled to the gate of the first transistor, and the body is coupled to the body of the second transistor,

wherein a signal transition provide at the gate of the first transistor is dependent only on a signal transition at the gate of the third transistor.

41. The high-voltage-tolerant interface circuit of claim 40 further comprising:

a fourth transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the I/O pad and the source is coupled to a third supply voltage; and

a fifth transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the first transistor, and the source is coupled to the third supply voltage.

42. The high-voltage-tolerant interface circuit of claim 41 wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are thick oxide devices.

43. The high-voltage-tolerant interface circuit of claim 41 further comprising:

a sixth transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the second transistor, the gate is coupled to the first supply voltage, and the source is coupled to a first node,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the sixth transistor.

44. A high-voltage-tolerant interface circuit for an integrated circuit comprising:

a first transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to an I/O pad and the source is coupled to first supply voltage;

a second transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the first transistor an the source is coupled to a second supply voltage; and

a third transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the second transistor, the source is coupled to the second supply, the gate is coupled to the gate of the first transistor, and the body is coupled to the body of the second transistor,

wherein a logic signal transition at the gate of the first transistor is logically dependent only on a logic signal transition at the gate of the third transistor.

45. The high-voltage-tolerant interface circuit of claim 44 further comprising:

a fourth transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the I/O pad and the source is coupled to a third supply voltage; and

a fifth transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the first transistor, and the source is coupled to the third supply voltage.

46. The high-voltage-tolerant interface circuit of claim 45 wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are thick oxide devices.

47. The high-voltage-tolerant interface circuit of claim 45 further comprising:

a sixth transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the second transistor, the gate is coupled to the first supply voltage, and the source is coupled to a first node,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the sixth transistor.

48. A high-voltage-tolerant interface circuit for an integrated circuit comprising:

a first pull-up device coupled between a first supply voltage and an I/O pad;

a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device; and

a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third pull-up device,

wherein a logic signal transition at the first control electrode of the first pull-up device is independent of logic signal transitions other than at the third control electrode of the third pull-up device.

49. The high-voltage-tolerant interface circuit of claim 48 further comprising:

a first pull-down device coupled between the output pad and a third supply voltage; and

a second pull-down device coupled between the first control electrode of the first pull-up device and the third supply voltage.

50. The high-voltage-tolerant interface circuit of claim 49 wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices.

51. The high-voltage-tolerant interface circuit of claim 49 further comprising:

a first pass device coupled between a first node and the second control electrode of the second pull up device, wherein a control electrode of the first pass device is coupled to the first supply voltage,

wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the first pass device.

52. A programmable logic integrated circuit comprising:

a plurality of logic array blocks;

a plurality of programmable interconnect, programmably coupled to the plurality of logic array blocks; and

at least one high-voltage-tolerant interface circuit block, programmably coupled to the programmable interconnect, comprising;

a first pull-up device couple between a first supply voltage and an I/O pad;

a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device; and

a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third pull-up device,

wherein a logic signal transit on at the first control electrode of the first pull-up device is independent of logic signal transitions other than at the third control electrode of the third pull-up device.

53. The programmable logic integrated circuit of claim 52 wherein the at least one high-voltage-tolerant interface circuit block further comprises:

a first pull-down device coupled between the output pad and a third supply voltage; and

a second pull-down device coupled between the first control electrode of the first pull-up device and the third supply voltage.

54. The programmable logic integrated circuit of claim 53 wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices.

55. The programmable logic integrated circuit of claim 53 wherein the at least one high-voltage-tolerant interface circuit block further comprises:

a first pass device coupled between a first node and the second control electrode of the second pull up device, wherein a control electrode of the first pass device is coupled to the first supply voltage,

wherein the first pull-up device, the second pull-up device, the third pull-up device, the first pull-down device, and the second pull-down device are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the first pass device.

56. A high-voltage-tolerant interface circuit for an integrated circuit comprising:

a first transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to an I/O pad and the source is coupled to a first supply voltage;

a second transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the first transistor and the source is coupled to a second supply voltage; and

a third transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the second transistor, the source is coupled to the second supply, the gate is coupled to the gate of the first transistor, and the body is coupled to the body of the second transistor,

wherein a logic signal transition at he gate of the first transistor is independent of logic signal transitions other than at the gate of he third transistor.

57. The high-voltage-tolerant interface circuit of claim 56 further comprising:

a fourth transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the I/O pad and the source is coupled to a third supply voltage; and

a fifth transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the first transistor, and the source is coupled to the third supply voltage.

58. The high-voltage-tolerant interface circuit of claim 57 wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are thick oxide devices.

59. The high-voltage-tolerant interface circuit of claim 57 further comprising:

a sixth transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the second transistor, the gate is coupled to the first supply voltage, and the source is coupled to a first node,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are thick oxide devices, and a gate oxide thickness of the thick oxide devices is greater than a gate oxide thickness of the sixth transistor.