CMOS inverter and standard cell using the same

• US 6,252,427 B1
• Filed: 06/15/1999
• Issued: 06/26/2001
• Est. Priority Date: 04/27/1999
• Status: Expired due to Term

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electric Corporation (Panasonic Holdings Corporation)
• Inventors: Domae, Shinichi, Ueda, Tetsuya
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/333,048
• Time in Patent Office: 742 Days
• Field of Search: 326/121, 326/81, 326/122, 326/101, 257/204, 257/202
• US Class Current: 326/121
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

To prevent a void from being formed in a CMOS inverter due to electromigration.

A power line 11 is connected to the source of a p-channel MOS transistor Tr1 via a first contact 12. A ground line 13 is connected to the source of an n-channel MOS transistor Tr2 via a second contact 14. One terminal of a first output signal line 15 is connected to the drain of the p-channel MOS transistor Tr1 via a third contact 16, while the other terminal thereof is connected to the drain of the n-channel MOS transistor Tr2 via a fourth contact 17. one terminal of a second output signal line 18 is connected to the fourth contact 17, while the other terminal thereof extends toward the output terminal of the inverter. A first path of an input signal line 19 is connected to the gate electrode 20 of the p-channel MOS transistor Tr1 via a fifth contact 21, while a second path thereof is connected to the gate electrode 20 of the n-channel MOS transistor Tr2 via a sixth contact 22.

Claims

1. A CMOS inverter comprising p- and n-channel MOS transistors, characterized by further comprising:

a power line connected to a source region of the p-channel MOS transistor via a first contact;

a ground line connected to a source region of the n-channel MOS transistor via a second contact;

a first output signal line, one terminal of the first output signal line being connected to a drain region of the p-channel MOS transistor via a third contact, the other terminal of the first output signal line being connected to a drain region of the n-channel MOS transistor via a fourth contact; and

a second output signal line, one terminal of the second output signal line being connected to the fourth contact, the other terminal of the second output signal line extending toward an output terminal of the inverter.

2. A standard cell made up of a plurality of CMOS inverters that are connected to each other, characterized in that the CMOS inverter as recited in claim 1 is used as a last-stage one of the CMOS inverters.

3. A standard cell made up of a plurality of CMOS inverters that are connected to each other, characterized in that the CMOS inverter as recited in claim 1 is used as one of the CMOS inverters, which is connected in parallel to other ones of the CMOS inverters at the output terminal thereof.

4. The CMOS inverter as recited in claim 1, characterized in that a line width at a portion of the power line, which is connected to the first contact, is larger than the width of the first contact.

5. The CMOS inverter as recited in claim 1, characterized in that a line width at a portion of the ground line, which is connected to the second contact, is substantially equal to the width of the second contact.

6. The CMOS inverter as recited in claim 1, characterized in that the first and second output signal lines are made of copper or a copper alloy.

7. A standard cell made up of a plurality of CMOS inverters that are connected to each other, characterized in that the CMOS inverter used as a last-stage one of the CMOS inverters comprises:

p- and n-channel MOS transistors, characterized in that the CMOS inverter further comprises;

a power line connected to a source region of the p-channel MOS transistor via a first contact;

a ground line connected to a source region of the n-channel MOS transistor via a second contact;

a first output signal line, one terminal of the first output signal line being connected to a drain region of the p-channel MOS transistor via a third contact, the other terminal of the first output signal line being connected to a drain region of the n-channel MOS transistor via a fourth contact; and

a second output signal line, one terminal of the second output signal line being connected to a portion of the first output signal line near the fourth contact, the other terminal of the second output signal line extending toward an output terminal of the inverter, and wherein

a current flows through the output terminal of the inverter into the fourth contact substantially without flowing through the first output signal line.

8. The standard cell as recited in claim 7 characterized in that the first and second output signal lines are made of copper or a copper alloy.

9. A standard cell made up of a plurality of CMOS inverters that are connected to each other, characterized in that the CMOS inverter used as one of the CMOS inverters, which is connected in parallel to other ones of the CMOS inverters at the output terminal thereof comprises:

p- and n-channel MOS transistors, characterized in that the CMOS inverter further comprises;

a power line connected to a source region of the p-channel MOS transistor via a first contact;

a ground line connected to a source region of the n-channel MOS transistor via a second contact;

a first output signal line, one terminal of the first output signal line being connected to a drain region of the p-channel MOS transistor via a third contact, the other terminal of the first output signal line being connected to a drain region of the n-channel MOS transistor via a fourth contact; and

a second output signal line, one terminal of the second output signal line being connected to a portion of the first output signal line near the fourth contact, the other terminal of the second output signal line extending toward an output terminal of the inverter, and wherein

a current flows through the output terminal of the inverter into the fourth contact substantially without flowing through the first output signal line.

10. The standard cell as recited in claim 9, characterized in that the first and second output signal lines are made of copper or a copper alloy.

11. A CMOS inverter characterized in that a line width at a portion of the power line, which is connected to a first contact, is larger than the width of the first contact comprises:

p- and n-channel MOS transistors, characterized in that the CMOS inverter further comprises;

a power line connected to a source region of the p-channel MOS transistor via a first contact;

a ground line connected to a source region of the n-channel MOS transistor via a second contact;

a first output signal line, one terminal of the first output signal line being connected to a drain region of the p-channel MOS transistor via a third contact, the other terminal of the first output signal line being connected to a drain region of the n-channel MOS transistor via a fourth contact; and

a second output signal line, one terminal of the second output signal line being connected to a portion of the first output signal line near the fourth contact, the other terminal of the second output signal line extending toward an output terminal of the inverter, and wherein

a current flows through the output terminal of the inverter into the fourth contact substantially without flowing through the first output signal line.

12. The CMOS inverter as recited in claim 11, characterized in that the first and second output signal lines are made of copper or a copper alloy.

13. A CMOS inverter characterized in that a line width at a portion of the ground line, which is connected to the second contact, is substantially equal to the width of the second contact comprises:

p- and n-channel MOS transistors, characterized in that the CMOS inverter further comprises;

a power line connected to a source region of the p-channel MOS transistor via a first contact;

a ground line connected to a source region of the n-channel MOS transistor via a second contact;

a first output signal line, one terminal of the first output signal line being connected to a drain region of the p-channel MOS transistor via a third contact, the other terminal of the first output signal line being connected to a drain region of the n-channel MOS transistor via a fourth contact; and

a second output signal line, one terminal of the second output signal line being connected to a portion of the first output signal line near the fourth contact, the other terminal of the second output signal line extending toward an output terminal of the inverter, and wherein

a current flows through the output terminal of the inverter into the fourth contact substantially without flowing through the first output signal line.

14. The CMOS inverter as recited in claim 13, characterized in that the first and second output signal lines are made of copper or a copper alloy.