Coincident complementary clock generator for logic circuits

• US 6,252,448 B1
• Filed: 11/23/1999
• Issued: 06/26/2001
• Est. Priority Date: 11/25/1998
• Status: Expired due to Fees

• Current Assignee: Innurvation IP LLC
• Original Assignee: Nanopower Technologies, Inc.
• Inventors: Schober, Robert C.
• Primary Examiner(s): Tran, Toan
• Assistant Examiner(s): NGUYEN, LINH M
• Application Number:
  US09/447,528
• Time in Patent Office: 581 Days
• Field of Search: 327/239, 327/256, 327/257, 327/258, 327/259, 327/170, 327/112
• US Class Current: 327/259
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 19/23 Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors
• CPC Class Codes: H03K 5/151 with two complementary outputs
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor to drive the output node strongly to achieve fast results. To reduce diffusion area, parallel logic is substantially eliminated and only series branches are used, in critical areas. This allows all pull-up transistors and/or all pull-down transistors to be formed from contiguous active areas. The D-to-Q path is reduced, and the clock is used to control the output. The clock becomes the dominant controller of the output when it is located closest to the output. Placing the clock devices closest to the clocked nodes reduces clock skew. The rising D response time and falling D response time are caused to be as close as possible to reduce the overall cycle time. To reduce parasitics in the circuit, complex-gates are used which are asymmetric. Even multiples of series branches per gate are used to share contacts and eliminate breaks in the layout diffusion. Adding complex-gates to a circuit while using asymmetric gates for smaller layouts achieves additional functionality. One component of the clock, along with the master drive circuit, is used to drive the slave latch of a flip-flop to avoid inserting additional gates into the logic of the fast output path. Reset and set circuitry is designed to be outside the critical path of the clock, and outside the slave latch, to provide rapid Q output response time to the clock and D inputs.

Claims

1. A circuit for generating a pair of coincident complementary clock signals comprising:

a first inverter outputting a first clock signal; and

a second inverter coupled to an output of the first inverter and outputting a second clock signal as a complement of the first clock signal, the second inverter comprising,

a pull up transistor coupled between an output node and a first supply node to pull the output node to a high logic level, and

a pull down transistor coupled between the output node and a second supply node to pull the output node to a low logic level, wherein a drive strength ratio of the pull-up transistor to the pull-down transistor has been selected to cause the first clock signal and the second clock signal to intersect during a transition at a level halfway between the high logic level and the low logic level.

2. A circuit as recited in claim 1, wherein the pull-down transistor is an n-channel and the pull-up transistor is a p-channel transistor, and wherein the pull-down transistor has a gate width that is greater than a gate width of the pull-up transistor.

3. A circuit as recited in claim 1, wherein the gate width of the pull-down transistor is at least twice the gate width of the pull-up transistor.

4. A circuit as recited in claim 3, wherein the pull-down transistor further comprises:

a first diffusion region formed in a substrate as a source of the pull-down transistor; and

a second diffusion region formed in the substrate as a drain of the pull-down transistor;

wherein the gate of the pull-down transistor is formed in a substantially loop-like pattern around the first diffusion or the second diffusion.

5. A circuit as recited in claim 1, wherein the pull-down transistor has a drive strength of at least three times a drive strength of the pull-up transistor.

6. A circuit as recited in claim 5, wherein the gate of the pull-down transistor is formed in a substantially loop-like pattern to substantially enclose the first diffusion region or the second diffusion region.

7. A circuit as recited in claim 5, wherein the gate of the pull-down transistor is formed in a substantially “

U”

shaped pattern around the first diffusion region or the second diffusion region.

8. A circuit as recited in claim 5, wherein the gate of the pull-down transistor is formed as a closed loop so as to completely enclose the first diffusion region or the second diffusion region as viewed from above a top surface of the substrate.

9. A circuit for generating a pair of coincident complementary clock signals comprising:

a first inverter outputting the first clock signal; and

a second inverter coupled to an output of the first inverter and outputting a second clock signal as a complement of the first clock signal, the second inverter comprising,

a p-channel pull-up transistor coupled between an output node and a first supply node to pull the output node to a high logic level, and

an n-channel pull-down transistor coupled between the output node and a second supply node to pull the output node to a low logic level, the pull-down transistor including,

a first diffusion region formed in a substrate as a source of a pull-down transistor;

a second diffusion region formed in the substrate as a drain of the pull-down transistor; and

a gate formed in a substantially loop-like pattern around the first diffusion or the second diffusion, such that a drive strength of the pull down transistor is at least three times a drive strength of the pull up transistor, such that the first and second clock signals intersect at approximately the midpoint between the high logic level and the low logic level during a transition of the first second clock signals.

10. A circuit as recited in claim 9, wherein the gate is formed in a substantially loop-like pattern to substantially enclose the first diffusion or the second diffusion.

11. A circuit as recited in claim 9, wherein the gate is formed in a substantially “

U”

-like pattern around the first diffusion or the second diffusion.

12. A circuit as recited in claim 9, wherein the gate is formed as a closed loop so as to completely enclose the first diffusion or the second diffusion from a point of view above the substrate.