Storage device having plural memory banks concurrently accessible, and access method therefor

• US 6,252,611 B1
• Filed: 07/23/1998
• Issued: 06/26/2001
• Est. Priority Date: 07/30/1997
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kondo, Tetsujiro
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US09/121,419
• Time in Patent Office: 1,069 Days
• Field of Search: 345/501-503, 345/521, 345/507, 345/508, 345/509, 345/515, 345/516, 382/232, 382/240, 382/302
• US Class Current: 345/536
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: H04N 19/39 involving multiple description coding [MDC], i.e. with separate layers being structured as independently decodable descriptions of input picture data
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/59 involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution

Abstract

A storage device and access method for performing hierarchical coding without the need for employing a circuit for a line delay, in addition to a memory for storing an image. Each of first and second memories is divided into two banks, a bank A and a bank B. A first layer pixel stored at the bank A in the first memory is read while a second layer pixel stored at the bank A in the second memory is read, and by subtracting the first layer pixel from the second layer pixel, a first pixel is finally determined and is written onto the bank A in the second memory that stored the second layer pixel. At the same time, a first layer pixel stored at the bank B in the first memory is read while a first layer pixel stored at the bank B in the second memory is read, and by summing these first layer pixels, the original second layer pixel is determined and the value stored at the bank B address in the second memory, which is the first layer pixel, is then rewritten to the original second layer pixel.

Claims

1. A storage device for storing an image, comprising:

a first memory area which has addresses corresponding to pixels for input image data and which is divided into a plurality of blocks, wherein the blocks are addressable on a block by block basis;

a second memory area having a smaller memory capacity than said first memory area, said second memory area being divided into the same number of blocks as the number of blocks included in said first memory area, wherein the blocks of said second memory area are addressable on a block by block basis;

an addressing module for concurrently addressing the blocks of said first memory area according to at least first and second address signals, while concurrently addressing each block in said second memory area according to only part of said first and second address signals; and

a read and write module for concurrently reading from addresses designated by said first and second address signals in the blocks of said first memory area, and for concurrently writing to addresses designated in the blocks in said first memory area designated by said first and second address signals.

2. A storage device according to claim 1, wherein said addressing module concurrently addresses corresponding locations in the blocks of said first memory area.

3. A storage device according to claim 1, wherein said read and write module determines the sum of data for a plurality of relatively high resolution pixels written in a plurality of addresses in said first memory area, corresponding to one address and one lower resolution pixel of said second memory area to write the sum onto the address of said second memory area as first image data derived from said input image data.

4. A storage device according to claim 1, wherein said first address signal and said second address signal respectively correspond to horizontal and vertical positions of a pixel for said input image data.

5. A storage device according to claim 1, wherein said second memory area has addresses corresponding to pixels for first image data derived from said input image data.

6. A storage device according to claim 1, further comprising a third memory area, wherein said first memory area stores relatively high resolution pixel data, said second memory area stores first lower resolution pixel data and said third memory area stores second lower resolution pixel data for pixels of reduced resolution relative to said first lower resolution data, said first and second lower resolution pixel data being derived from said input image data.

7. A storage device for storing an image, comprising:

a first memory which has addresses corresponding to pixels for input image data and a memory area which is divided into a plurality of blocks, wherein the blocks are addressable on a block by block basis;

a second memory which has addresses corresponding to pixels for first image data derived from said input image data and a memory area which is divided into the same number of blocks as the number of blocks included in said first memory, wherein the blocks of said second memory are addressable on a block by block basis;

an addressing module for concurrently addressing the blocks of said first memory according to at least first and second address signals corresponding to respective horizontal and vertical positions of a pixel of said input image data, while concurrently addressing each block in said second memory according to at least part of said first and second address signals; and

a read and write module for concurrently reading from addresses, designated by said first and second address signals, in the plurality of blocks in said first memory, and for concurrently writing from addresses in the plurality of blocks in said first memory designated by said first and second address signals;

wherein said first memory has a memory capacity corresponding to the value which is obtained by subtracting the number of addresses in said second memory from the number of pixels of one display screen for said input image data.

8. A storage device according to claim 7, wherein said read and write module reads said input image data stored at the address in said first memory, designated by said first and second address signals, while reading said first processed data stored at the address in said second memory, designated by part of said first and second address signals,

computes second data by processing both said input image data and said first processed data, and

writes said second processed data onto the address in said second memory which stored said first processed data.

9. A storage device according to claim 8, wherein said addressing module generates a predetermined address signal from said first and second address signals and performs addressing according to said predetermined address signal and said first and second address signals;

said read and write module reads said input image data stored at an address of a predetermined block in said first memory, designated by said first and second address signals while reading said first processed data stored at an address of the block in said second memory, designated by part of said first and second address signals and corresponding to the predetermined block in said first memory,

computes said second processed data by processing said input image data and said first processed data, and

writes said second processed data onto the address in said second memory which stored said first processed data,

while, at the same time, said read and write module reads said input image data stored in the other block in said first memory, designated by said predetermined address signal while reading said second processed data stored in the block in said second memory designated by part of said predetermined address signal, and corresponding to the other block in said first memory,

computes said first processed data by processing said input image data and said second processed data, and

writes said first processed data onto the address in said second memory which stored said second processed data.

10. A method of accessing a storage device for storing an image, wherein the storage device comprises a first memory area which has addresses corresponding to pixels for input image data and which is divided into a plurality of blocks, and wherein said blocks are addressable on a block by block basis, said method comprising:

concurrently addressing the blocks in said first memory area according to at least first and second address signals;

concurrently addressing blocks in a second memory area of said storage device having less memory capacity than said first memory area, according to only part of said first and second address signals;

concurrently writing to addresses designated by said first and second address signals, in the blocks in the first memory area; and

,

concurrently reading from addresses designated by said first and second address signals, in the blocks in the first memory area.

11. A storage medium comprising:

a first memory area for storing less than a full display screen of only high resolution data;

at least a second memory area, separate from said first memory area and having less storage capacity than said first memory area, for storing an entire display screen of lower resolution data corresponding to said high resolution data;

wherein a full display screen of high resolution data is obtained from said storage medium by reading the high resolution data stored in said first memory area to obtain high resolution data for a first portion of the pixels of the full display screen, and reading the lower resolution data stored in at least the second memory area and converting the lower resolution data to high resolution data for a second portion of the pixels of the full display screen, said first and second portions being combined to obtain said full display screen of high resolution data.

12. The storage medium of claim 11 wherein each pixel of the lower resolution data corresponds to four pixels of the high resolution data, and said first portion of the pixels is three quarters of the pixels of a full display screen.

13. The storage medium of claim 11 wherein each of said first and second memory areas is divided into a plurality of concurrently accessible blocks.

14. The storage medium of claim 11, further comprising an addressing module that concurrently addresses blocks in the first memory area according to first and second address signals, and concurrently addresses blocks in the second memory area according to only part of the same first and second address signals used to address said blocks in the first memory area.