Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse
First Claim
1. A non-volatile semiconductor memory device comprising:
- a memory cell array having cell strings each of which is constituted of a plurality of memory cells connected in series, each of said memory cells having at least a control gate; and
a control circuit that, at a time of programming, applies a write voltage pulse to the control gate of a memory cell selected from the plurality of memory cells constituting the cell strings, and that, at the time of programming, applies a transfer voltage pulse to non-selected memory cells, wherein said control circuit changes a signal level of the transfer voltage pulse prior to the change in a signal level of the write voltage pulse and wherein said control circuit controls the timings of the write voltage pulse and the transfer voltage pulse in such a manner that the transfer voltage pulse falls when the write voltage pulse is at a high level.
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Abstract
A nonvolatile semiconductor memory device comprises a memory cell array having plural electrically erasable memory cells including a gate, a source, a drain, and an electric charge accumulation layer each disposed in a matrix form. A data writing section writes data into memory cells in this memory cell array. A data reading section reads out data in memory cells of the memory cell array. A data erasing section erases data in memory cells of the memory cell array. A control section controls, when applying a first signal to the gate in a specified memory inhibited of writing and applying a second signal to a node capacitively coupled to at least one of source and drain, in writing data into the memory cells, so that the second signal may fall later than the first signal.
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Citations
10 Claims
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1. A non-volatile semiconductor memory device comprising:
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a memory cell array having cell strings each of which is constituted of a plurality of memory cells connected in series, each of said memory cells having at least a control gate; and
a control circuit that, at a time of programming, applies a write voltage pulse to the control gate of a memory cell selected from the plurality of memory cells constituting the cell strings, and that, at the time of programming, applies a transfer voltage pulse to non-selected memory cells, wherein said control circuit changes a signal level of the transfer voltage pulse prior to the change in a signal level of the write voltage pulse and wherein said control circuit controls the timings of the write voltage pulse and the transfer voltage pulse in such a manner that the transfer voltage pulse falls when the write voltage pulse is at a high level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A non-volatile semiconductor memory device comprising:
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a memory cell array having cell strings arranged in a matrix form, each of said cell strings constituted of a plurality of memory cells which include control gates, sources and drains and are connected in series in such a manner that adjacent ones of the memory cells share one source and one drain;
a plurality of bit lines connected to one end of each of the cell strings and arranged in a column direction of the memory cell array;
a source line connected to the other end of each of the cell strings; and
a control circuit that, at a time of programming, applies a write voltage pulse to the control gate of memory cell selected from the plurality of memory cells constituting the cell strings, and that, at the time of programming, applies a transfer voltage pulse to non-selected memory cells, wherein said control circuit changes a signal level of the transfer voltage pulse prior to the change in a sismal level of the write voltage pulse and wherein said control circuit controls the timings of the write voltage pulse and the transfer voltage pulse in such a manner that the transfer voltage pulse falls when the write voltage pulse is at a high level. - View Dependent Claims (10)
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Specification