Automatic program disturb with intelligent soft programming for flash cells
First Claim
1. A method of erasing a flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) device which includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, comprising the steps of:
- (a) applying an erase pulse to the plurality of memory cells;
(b) overerase verifying the plurality of memory cells to determine if there are overerased memory cells in the plurality of memory cells;
(c) applying an overerase correction pulse to a bitline to which an overerased memory cell is attached;
(d) repeating steps (b) and (c) until all of the plurality of memory cells verify as not being overerased;
(e) erase verifying the plurality of memory cells to determine if there are undererased memory cells in the plurality of memory cells;
(f) applying another erase pulse to the plurality of memory cells if there are undererased memory cells in the plurality of memory cells;
(g) repeating steps (b) through (f) until all of the plurality of memory cells verify as not being undererased;
(h) soft program verifying the plurality of memory cells to determine if there are memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value; and
(i) applying a soft programming pulse to those memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value.
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Accused Products
Abstract
A method of erasing a flash electrically-erasable programmable read-only memory (EEPROM) device is provided which includes a plurality of memory cells. An erase pulse is applied to the plurality of memory cells. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached. This cycle is repeated until all cells verify as not being overerased. The plurality of memory cells is erase verified and another erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle is repeated until all cells verify as not being undererased. After erase verify is completed, the plurality of memory cells is soft program verified and a soft programming pulse is applied to the those memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value. This cycle is repeated until all of those memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value are brought above the pre-defined minimum value. The erase method is considered to be finished when there are no memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value.
109 Citations
5 Claims
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1. A method of erasing a flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) device which includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, comprising the steps of:
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(a) applying an erase pulse to the plurality of memory cells;
(b) overerase verifying the plurality of memory cells to determine if there are overerased memory cells in the plurality of memory cells;
(c) applying an overerase correction pulse to a bitline to which an overerased memory cell is attached;
(d) repeating steps (b) and (c) until all of the plurality of memory cells verify as not being overerased;
(e) erase verifying the plurality of memory cells to determine if there are undererased memory cells in the plurality of memory cells;
(f) applying another erase pulse to the plurality of memory cells if there are undererased memory cells in the plurality of memory cells;
(g) repeating steps (b) through (f) until all of the plurality of memory cells verify as not being undererased;
(h) soft program verifying the plurality of memory cells to determine if there are memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value; and
(i) applying a soft programming pulse to those memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value. - View Dependent Claims (2, 3, 4, 5)
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Specification
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- Resources
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Current AssigneeMonterey Research, LLC (Vector Capital Corporation)
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Original AssigneeAdvanced Micro Devices, Inc.
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InventorsChang, Chi, Fastow, Richard, Haddad, Sameer S., Cleveland, Lee E.
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Primary Examiner(s)Tran, Andrew Q.
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Application NumberUS09/692,881Time in Patent Office246 DaysField of Search365/185.22, 365/185.29, 365/185.3, 365/185.33, 365/185.02, 365/185.11, 365/185.12, 365/185.13US Class Current365/185.22CPC Class CodesG11C 16/16 for erasing blocks, e.g. ar...
