Dummy wordline circuitry

• US 6,252,814 B1
• Filed: 04/29/1999
• Issued: 06/26/2001
• Est. Priority Date: 04/29/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation, Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: International Business Machines Corporation
• Inventors: Taylor, Scott A., Tran, Tam Minh
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/303,347
• Time in Patent Office: 789 Days
• Field of Search: 365/210, 365/230.06, 365/233, 365/185.2
• US Class Current: 365/210.1
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

Two separate dummy wordlines, a read dummy wordline and a write dummy wordline, are implemented within a memory array to provide for higher frequency operation of read and write cycles within the memory array. The two dummy wordlines are utilized to activate and deactivate the wordline enable signal for the read and write portions of an access. Such an access can be a read/swap cycle.

Claims

1. A memory array comprising:

a plurality of bitcells arranged in a plurality of rows and columns;

a first dummy wordline for accessing a first one of the plurality of rows of bitcells and concurrently a first one of the plurality of columns of bitcells; and

a second dummy wordline for accessing a second one of the plurality of rows of bitcells and concurrently a second one of the plurality of columns of bitcells.

2. The memory array as recited in claim 1, wherein the first one of the plurality of rows and the first one of the plurality of columns of bitcells and the second one of the plurality of rows and the second one of the plurality of columns of bitcells do not store writeable data for use by circuitry accessing the memory array.

3. The memory array as recited in claim 2, further comprising a third-wordline for accessing one of the plurality of rows of bitcells, wherein the third one of the plurality of rows of bitcells do store data for use by circuitry accessing the memory array.

4. The memory array as recited in claim 1, wherein the first dummy wordline is activated during a read access of a read/swap cycle, and the second dummy wordline is activated during a write access of the read/swap cycle.

5. The memory array as recited in claim 2, further comprising:

a first dummy bitline receiving outputs of selected bitcells in the first one of the plurality of the columns of bitcells accessed by the first dummy wordline; and

a second dummy bitline receiving outputs of selected bitcells in the second one of the plurality of the columns of bitcells accessed by the second dummy wordline.

6. The memory array as recited in claim 5, wherein the first and second dummy bitlines are used in logic operable to generate a wordline enable signal in response to the first and second dummy bitline, a read enable signal, a write enable signal and a read and a write control signal.

7. The memory array as recited in claim 5, further comprising:

a first dummy wordline driver coupled to the first dummy wordline;

a second dummy wordline driver coupled to the second dummy wordline;

wherein the first dummy wordline driver is operable to generate the first dummy wordline in response to the read control signal, the read enable signal and the wordline enable signal and the second dummy wordline driver is operable to generate said second dummy wordline in response to the write control signal, the write enable signal and the wordline enable signal.

8. The memory array as recited in claim 7, wherein a read and a write for the memory array within a clock cycle are timed by the wordline enable signal received by the first and second dummy wordline drivers and circuits employed in the read and write for the memory array are controlled by the wordline enable signal, whereby the write following the read may commence asynchronous with the clock edges.

9. A data processing system comprising:

a processor coupled by a bus to an input device, and output device, and a memory device, wherein the memory device further comprises;

a plurality of bitcells arranged in a plurality of rows and columns;

a first dummy wordline for accessing a first one of the plurality of rows of bitcells and concurrently a first one of the plurality of columns of bitcells; and

a second dummy wordline for accessing a second one of the plurality of rows of bitcells and concurrently a second one of the plurality of columns of bitcells.

10. The data processing system as recited in claim 9, wherein the first one of the plurality of rows and the first one of the plurality of columns of bitcells and the second one of the plurality of rows and the second one of the plurality of columns of bitcells do not store writeable data for use by circuitry accessing the memory array.

11. The data processing system as recited in claim 10, further comprising a third wordline for accessing one of the plurality of rows of bitcells, wherein the third one of the plurality of rows of bitcells do store data for use by circuitry accessing the memory device.

12. The data processing system as recited in claim 11, wherein the first dummy wordline is activated during a read access of a read/swap cycle, and the second dummy wordline is activated during a write access of the read/swap cycle.

13. The data processing system as recited in claim 12, further comprising:

a first dummy bitline receiving outputs of selected bitcells in the first one of the plurality of the columns of bitcells accessed by the first dummy wordline; and

a second dummy bitline receiving outputs of selected bitcells in the second one of the plurality of the columns of bitcells accessed by the second dummy wordline.

14. The data processing system as recited in claim 13, further comprising:

a first dummy wordline driver coupled to the first dummy wordline;

a second dummy wordline driver coupled to the second dummy wordline;

wherein the first dummy wordline driver is operable to generate the first dummy wordline in response to the read control signal the read enable signal and the wordline enable signal and the second dummy wordline driver is operable to generate said second dummy wordline in response to the write control signal, the write enable signal and the wordline enable signal.