Method and apparatus for bridging a plurality of buses and handling of an exception event to provide bus isolation

• US 6,253,250 B1
• Filed: 06/28/1999
• Issued: 06/26/2001
• Est. Priority Date: 06/28/1999
• Status: Expired due to Term

• Current Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Original Assignee: Telocity, Inc. (AT&T, Inc.)
• Inventors: Grundy, Kevin P., Evans, Keith M.
• Primary Examiner(s): Maung, Zarni
• Assistant Examiner(s): Prieto, Beatriz
• Application Number:
  US09/340,563
• Time in Patent Office: 729 Days
• Field of Search: 709/253, 709/225, 709/229, 709/212, 709/224, 709/208, 709/209, 709/216, 710/22, 710/23, 710/27, 710/28, 710/54, 710/37, 710/38, 714/43, 714/39, 714/44, 714/49
• US Class Current: 709/253
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A bus bridge coupled between two bridges providing bus exception event isolation and address/data translation. In one embodiment the bus bridge includes two direct memory access (DMA) engines and a first-in-first-out (FIFO) buffer interface between the DMA engines to provide the bus exception isolation. The DMA engines and FIFOs also enable a packet based message passing architecture, which eliminates the need for address translation and also handles data reordering.

Claims

1. A bus bridge coupled to transfer data between a first bus and a second bus, comprising:

a first bus exception domain coupled to the first bus such that a bus exception event that occurs in the first bus is limited to the first bus exception domain;

a second bus exception domain coupled between the first bus exception domain and the second bus such that a bus exception event that occurs in the second bus is limited to the second bus exception domain;

a first bus exception monitor included in the first bus exception domain to monitor for the bus exception event that occurs in the second bus; and

a second bus exception monitor included in the second bus exception domain to monitor for the bus exception event that occurs in the first bus.

2. The bus bridge described in claim 1 further comprising:

a first direct memory access (DMA) engine included in the first bus exception domain and coupled to the first bus; and

a second DMA engine included in the domain bus exception domain and coupled between the first DMA engine and the second bus.

3. The bus bridge described in claim 2 further comprising:

a first buffer included in the first bus exception domain coupled between the first DMA engine and the second DMA engine such that data is to be transferred from the first bus through the first buffer to the second bus; and

a second buffer included in the second bus exception domain coupled between the second DMA engine and the first DMA engine such that data is to be transferred from the second bus through the second buffer to the first bus.

4. The bus bridge described in claim 3 wherein the first and second buffers are first in first out (FIFO) buffers.

5. The bus bridge described in claim 2 wherein the first DMA engine includes a first transmit descriptor address to point to a first transmit descriptor to be accessed from a first memory over the first bus to transfer data from the first bus to the second bus, the first transmit descriptor to point to a first transmit data buffer in the first memory.

6. The bus bridge described in claim 2 wherein the first DMA engine includes a first receive descriptor address to point to a first receive descriptor to be accessed from a first memory over the first bus to transfer data from the second bus to the first bus, the first receive descriptor to point to a first receive data buffer in the first memory.

7. The bus bridge described in claim 2 wherein the second DMA engine includes a second transmit descriptor address to point to a second transmit descriptor to be accessed from a second memory over the second bus to transfer data from the second bus to the first bus, the second transmit descriptor to point to a second transmit data buffer in the second memory.

8. The bus bridge described in claim 2 wherein the second DMA engine includes a second receive descriptor address to point to a second receive descriptor to be accessed from a second memory over the second bus to transfer data from the first bus to the second bus, the second receive descriptor to point to a second receive data buffer in the second memory.

9. The bus bridge described in claim 3 wherein data to be transferred from the first bus through the first buffer to the second bus is formatted as a data stream with embedded frame markers free of memory addressing information.

10. The bus bridge described in claim 9 wherein the embedded frame markers include a start of frame marker and an end of frame marker.

11. The bus bridge described in claim 3 wherein data to be transferred from the second bus through the second buffer to the first bus is formatted as a data stream with embedded frame markers free of memory addressing information.

12. The bus bridge described in claim 5 wherein a lost in transit indicator is to be set in the first transmit descriptor if the bus exception event occurs in the second bus during the transfer of data from the first bus to the second bus.

13. The bus bridge described in claim 6 wherein an invalid data indicator is to be set in the first receive descriptor if the bus exception event occurs in the second bus during the transfer of data from the second bus to the first bus.

14. The bus bridge described in claim 1 wherein at least one of the first and second buses is a peripheral component interconnect (PCI) bus.

15. The bus bridge described in claim 1 wherein the bus exception event is a bus reset event.

16. A method of transferring data between a first bus and a second bus, the method comprising the steps of:

reading data from a first memory over the first bus;

writing the data read from the first memory into a second memory over the second bus;

isolating from the second bus a bus exception event that occurs in the first bus; and

setting an invalid data indicator in a receive descriptor in the second memory if the bus exception event occurs in the first bus during the step of reading the data from the first memory.

17. The method of transferring data between the first bus and the second bus described in claim 16 including the additional steps of:

isolating from the first bus a bus exception event that occurs in the second bus; and

setting a lost in transit indicator in a transmit descriptor in the first memory if the bus exception event occurs in the second bus during the step of writing the data read from the first memory.

18. The method of transferring data between the first bus and the second bus described in claim 16 including the additional steps of:

reading data from the second memory over the second bus;

writing the data read from the second memory into the first memory over the first bus;

isolating from the first bus a bus exception event that occurs in the second bus; and

setting an invalid data indicator in a receive descriptor in the first memory if the bus exception event occurs in the second bus during the step of reading the data from the second memory.

19. The method of transferring data between the first bus and the second bus described in claim 18 including the additional step of setting a lost in transit indicator in a transmit descriptor in the second memory if the bus exception event occurs in the first bus during the step of writing the data read from the second memory.

20. The method of transferring data between the first bus and the second bus described in claim 16 wherein the step of setting the invalid data indicator in the receive descriptor in the second memory if the bus exception event occurs in the first bus includes the step of monitoring for the bus exception event that occurs in the first bus.

21. The method of transferring data between the first bus and the second bus described in claim 18 wherein the step of setting the invalid data indicator in the receive descriptor in the first memory if the bus exception event occurs in the second bus includes the step of monitoring for the bus exception event that occurs in the second bus.

22. The method of transferring data between the first bus and the second bus described in claim 16 wherein at least one of the first and second buses is a peripheral component interconnect (PCI) bus.

23. The method of transferring data between the first bus and the second bus described in claim 16 wherein the bus exception event that occurs in the first bus is a bus reset event.

24. The method of transferring data between the first bus and the second bus described in claim 16 wherein the step of reading data from the first memory over the first bus includes the steps of:

building a transmit descriptor in the first memory, the transmit descriptor to describe the data to be read from the first memory;

loading an address into a direct memory access (DMA) engine of the transmit descriptor in first memory;

enabling the DMA engine to become master of the first bus to read the data from the first memory.

25. The method of transferring data between the first bus and the second bus described in claim 24 including the additional step of writing the data read the first memory into a first in first out (FIFO) buffer, the step of writing the data from the first memory into the FIFO to be performed before the step of writing the data read from the first memory into the second memory over the second bus.

26. The method of transferring data between the first bus and the second bus described in claim 25 including the additional step of embedding frame markers into the data written into the FIFO, the embedded frame markers include a start of frame marker and an end of frame marker.

27. The method of transferring data between the first bus and the second bus described in claim 26 including the step of scanning the FIFO for the start of frame marker such that the step of writing the data read from the first memory into a second memory over the second bus is performed after the start of frame marker is scanned from the FIFO.

28. The method of transferring data between the first bus and the second bus described in claim 16 wherein the step of writing the data read from the first memory into the second memory over the second bus includes the steps of:

allocating space in the second memory to write the data read from the first memory;

building a receive descriptor in the second memory, the receive descriptor to describe where space has been allocated to write the data read from the first memory;

loading an address into a direct memory access (DMA) engine of the receive descriptor in second memory;

enabling the DMA engine to become master of the second bus to write the data read from the first memory.

29. An apparatus comprising:

a first memory coupled to a first bus;

a first direct memory access (DMA) engine coupled to the first bus;

a first first in first out (FIFO) buffer coupled to the first DMA engine such that the first DMA engine is to read data from the first memory through the first bus into the first FIFO;

a second DMA engine coupled between the first FIFO and a second bus; and

a second memory coupled to the second bus such that the second DMA engine is to read the data from the first FIFO and write the data into the second memory.

30. The apparatus of claim 29 further comprising a second FIFO coupled between the first and second DMA engines such that the second DMA engine is to read data from the second memory through the second bus into the second FIFO and the first DMA engine is to read the data from the second FIFO and write the data into the first memory.

31. The apparatus of claim 30 further comprising:

a first bus exception domain coupled to the first bus, the first bus exception domain including the first DMA engine and the first FIFO; and

a second bus exception domain coupled between the first bus exception domain and the second bus, the second bus exception domain including the second DMA engine and the second FIFO, wherein the a bus exception event occurring in either one of the first and second bus exception domains is isolated from occurring in the other one of the bus exception domains.

32. The apparatus of claim 31 further comprising:

a first bus exception monitor included in the first DMA engine to monitor for a bus exception event in the second bus exception domain; and

a second bus exception monitor included in the second DMA engine to monitor for a bus exception event in the first bus exception domain.