Memory control using memory state information for reducing access latency

• US 6,253,297 B1
• Filed: 10/13/1998
• Issued: 06/26/2001
• Est. Priority Date: 04/29/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: dʼInverno, Dominique Benoît Jacques, Lasserre, Serge, Chauvel, Gérard
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US09/170,834
• Time in Patent Office: 987 Days
• Field of Search: 711/111, 711/154, 711/156, 711/167, 365/189.07, 365/203, 365/221, 365/233
• US Class Current: 711/167
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A memory controller circuit (18a) for coupling to a memory (24), where the memory has a plurality of rows. The memory controller circuit includes circuitry (28) for receiving signals representative of requests to access the memory. Given these signals, a first such signal representative of a first request to access the memory is received by the circuitry for receiving and comprises a first address in the memory, and a second signal representative of a second request to access the memory is received by the circuitry for receiving after the first signal and comprises a second address in the memory. The memory controller circuit also includes determining circuitry (30, RAn, AC₁₃ Bn₁₃ ROW, C_B_Rn) for determining whether the second address is directed to a same one of the plurality of rows as the first address. Still further, the memory controller circuit includes circuitry (30) for issuing control signals to the memory in response to receiving signals representative of requests to access the memory. These control signals cause a first memory access to occur in response to the first request and a second memory access to occur in response to the second request. Lastly, in response to the determining circuitry determining that the second address is directed to the same one of the plurality of rows as the first address, the circuitry for issuing control signals issues control signals to the memory such that the same one of the plurality of rows is maintained active between the first and second access.

Claims

1. A memory controller circuit for coupling to a memory having a plurality of banks and rows, comprising:

circuitry for receiving signals representative of requests to access the memory, wherein a first signal representative of a first request to access the memory is received by the circuitry for receiving and comprises a first address in the memory and wherein a second signal representative of a second request to access the memory is received by the circuitry for receiving after the first signal and comprises a second address in the memory;

determining circuitry for determining whether the second address is directed to a same one of the plurality of rows as the first address, the determining circuitry includes circuitry for indicating state information of the memory said circuitry comprising a plurality of address registers, wherein each of the plurality of address registers stores an address of an active row corresponding to a different one of the plurality of banks in the memory;

circuitry for issuing control signals to the memory in response to receiving signals representative of requests to access the memory, the control signals causing a first memory access to occur in response to the first request and causing a second memory access to occur in response to the second request; and

wherein in response to the determining circuitry determining that the second address is directed to the same one of the plurality of rows as the first address, the circuitry for issuing control signals issues control signals to the memory such that the same one of the plurality of rows is maintained active between the first and second access.

2. The memory controller of claim 1 wherein in response to the determining circuitry determining that the second address is directed to the same one of the plurality of rows as the first address, the circuitry for issuing control signals issues control signals to the memory such that the same one of the plurality of rows is maintained active by not precharging the same one of the plurality of rows between the first and second access.

3. The memory controller of claim 1 wherein the first request to access the memory and the second request to access the memory are from a same circuit.

4. The memory controller of claim 1 wherein the first request to access the memory and the second request to access the memory are from a different circuit.

5. The memory controller of claim 1 wherein the first request to access the memory and the second request to access the memory are from circuits selected from a group consisting of a central processing unit, a digital signal processor, a video controller, and a peripheral computing device.

6. The memory controller of claim 1 wherein the circuitry for indicating state information of the memory further comprises a plurality of valid registers corresponding to each of the plurality of address registers, wherein each of the plurality of valid registers presents an indicator representing whether the corresponding address register is storing a valid address.

7. The memory controller of claim 6 wherein the circuitry for indicating state information of the memory further comprises a plurality of bank registers corresponding to each of the plurality of banks, wherein each of the plurality of bank registers presents an indicator representing whether the corresponding bank is currently accessed.

8. The memory controller of claim 1 wherein the circuitry for indicating state information of the memory further comprises a plurality of bank registers corresponding to each of the plurality of banks, wherein each of the plurality of bank registers presents an indicator representing whether the corresponding bank is currently accessed.

9. The memory controller of claim 1 wherein the circuitry for issuing control signals to the memory in response to receiving requests to access the memory issues control signals causing overhead cycles for the second memory access to occur during at least one data transfer cycle of the first memory access.

10. The memory controller of claim 1 wherein the circuitry for issuing control signals to the memory in response to receiving requests to access the memory issues control signals for the second memory access to occur in the next clock cycle following a last data cycle of the first memory access.

11. The memory controller of claim 10:

wherein the second memory access comprises a read memory access; and

wherein the circuitry for issuing control signals aligns the control signals in response to CAS latency.

12. The memory controller of claim 11 wherein the circuitry for issuing control signals aligns the control signals in response to CAS latency as detected in response to system clock speed.

13. The memory controller of claim 1 wherein the second request is received by the memory controller after a final transfer cycle of the first memory access.

14. The memory controller of claim 1 wherein the memory comprises a dynamic random access memory.

15. The memory controller of claim 1 wherein the memory comprises a synchronous dynamic random access memory.

16. A computing system, comprising:

a memory having a plurality of rows;

circuitry for issuing requests to access the memory; and

a memory controller, comprising;

circuitry for receiving signals representing the requests to access the memory, wherein a first signal representative of a first request to access the memory is received by the circuitry for receiving and comprises a first address in the memory and wherein a second signal representative of a second request to access the memory is received by the circuitry for receiving after the first signal and comprises a second address in the memory;

determining circuitry for determining whether the second address is directed to a same one of the plurality of rows as the first address, the determining circuitry includes circuitry for indicating state information of the memory said circuitry comprising a plurality of address registers, wherein each of the plurality of address registers stores an address of an active row corresponding to a different one of the plurality of banks in the memory;

circuitry for issuing control signals to the memory in response to receiving signals representing requests to access the memory, the control signals causing a first memory access to occur in response to the first request and causing a second memory access to occur in response to the second request; and

wherein in response to the determining circuitry determining that the second address is directed to the same one of the plurality of rows as the first address, the circuitry for issuing control signals issues control signals to the memory such that the same one of the plurality of rows is maintained active between the first and second access.

17. The computing system of claim 16 wherein the circuitry for issuing requests to access the memory is selected from a group consisting of a central processing unit, a digital signal processor, a video controller, and a peripheral computing device.

18. The computing system of claim 16 wherein the circuitry for indicating state information of the memory further comprises a plurality of valid registers corresponding to each of the plurality of address register, wherein each of the plurality of valid registers presents an indicator representing whether the corresponding address register is storing a valid address.

19. The computing system of claim 18 wherein the circuitry for indicating state information of the memory further comprises a plurality of bank registers corresponding to each of the plurality of banks, wherein each of the plurality of bank registers presents an indicator representing whether the corresponding bank is currently accessed.

20. The computing system of claim 16 wherein the circuitry for indicating state information of the memory further comprises a plurality of bank registers corresponding to each of the plurality of banks, wherein each of the plurality of bank registers presents an indicator representing whether the corresponding bank is currently accessed.

21. The computing system of claim 16 and further comprising a direct memory access controller for receiving the requests to access the memory including the first request and the second request, and for issuing in response to the requests to access the memory corresponding signals which include the first signal and the second signal.

22. The computing system of claim 16 and further comprising:

a direct memory access controller responsive to the requests to access the memory, and comprising;

circuitry for associating, for each of the requests to access the memory, an initial priority value corresponding to the request;

circuitry for changing the initial priority value for selected ones of the requests to access the memory to a different priority value; and

circuitry for outputting a signal to the memory controller and representing the request having a highest priority value.

23. The computing system of claim 22 wherein the direct memory access controller further comprises:

circuitry for detecting that a received request to access the memory is a burst access request; and

conversion circuitry for converting the burst access request into a plurality of burst access requests.

24. The computing system of claim 16 and further comprising a direct memory access controller responsive to the requests to access the memory, and comprising:

circuitry for detecting that a received request to access the memory is a burst access request; and

conversion circuitry for converting the burst access request into a plurality of burst access requests.