Timing generator

• US 6,253,360 B1
• Filed: 04/05/1999
• Issued: 06/26/2001
• Est. Priority Date: 08/06/1997
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Yoshiba, Kazumichi
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/269,985
• Time in Patent Office: 813 Days
• Field of Search: 716/6, 716/5, 716/1, 703/19, 327/144
• US Class Current: 327/144
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: G06F 1/025 for functions having two-valued amplitude, e.g. Walsh functions

Abstract

A timing generator capable of setting data indicating that a timing signal is to be generated in the next cycle, even in the case of generating test pattern signals in multiple way system is provided. In each of clock data processing circuits of N timing generators, N being an integer of 2 or greater than 2, are provided a multiplier for multiplying by N a value of period data read out of period data memory of the associated clock data processing circuit, a subtracter for performing a subtraction between the period data multiplied by N by the multiplier and clock data supplied from a main controller, and means for providing, only in the case that N or more period data are in succession, the period of each of the period data being a constant, a control signal to the associated clock data processing circuit, the control signal enabling a subtraction value outputted from an output terminal of the associated subtracter and a next flag outputted from a carry signal output terminal of the associated subtracter when a value of the clock data is greater than that of the period data multiplied by N to be stored in the memory of the associated clock generator, the next flag representing that a clock is to be generated in the next cycle.

Claims

1. A timing generator means comprising a plurality of N timing generators, N being an integer of 2 or greater than 2, each of the N timing generators including a clock generator, a period generator and a clock data processing circuit, said timing generator means being arranged such that a timing of generation of a clock outputted from each of said clock generators is controlled based on data previously set in a memory provided in each of said clock generators, thereby to generate a clock at a desired timing from each of the clock generators, each of said clock data processing circuits including:

a multiplier for multiplying by N a value of period data read out of period data memory of the associated clock data processing circuit; and

a subtracter for performing a subtraction between the period data multiplied by N by said multiplier or the period data read out of the period data memory and clock data supplied from the outside,

said timing generator means further including;

means for supplying, only in the case that N or more period data are in succession, the period of each of said period data being a constant, period data read out of said period data memory to each of said multipliers to multiply the period data by N, thereby providing a control signal to each of said clock data processing circuits, said control signal enabling a subtraction value outputted from an output terminal of each of said subtracters and a next flag outputted from a carry signal output terminal of each of said subtracters when a value of the clock data is greater than that of the period data multiplied by N to be stored in the memory of each of said clock generators, said next flag representing that a clock is to be generated in the next cycle, and

whereby in the case of operating each timing generator in N way system, when clock data for generating a clock at a desired timing point in the next cycle is supplied together with period data read out of the associated period data memory, a next flag outputted from the carry signal output terminal of the associated subtracter and the subtraction value outputted from the output terminal of the associated subtracter can be stored in the memory of the associated clock generator.

2. The timing generator means according to claim 1, wherein the period data memory of each of said clock data processing circuits has various kinds of period data previously set from a main controller, each of said subtracters performs a subtraction between period data read out of the associated period data memory or period data multiplied by N by the associated multiplier and clock data supplied from the main controller, and said next flag is outputted from the carry signal output terminal of the associated subtracter when a value of the clock data is greater than that of the period data multiplied by N.

3. The timing generator means according to claim 1, wherein there are provided short circuits each for bypassing the associated multiplier of said multipliers, and switching means each for turning on/off the associated short circuit of said short circuits, and wherein only in the case that N or more period data are in succession, the period of each of said period data being a constant, each of said switching means turns off the associated short circuit.

4. The timing generator means according to claim 1, wherein based on timing set information supplied from a pattern generator to the associated clock data processing circuit of said clock data processing circuits, period data is read out of the period data memory of the associated clock data processing circuit, said period data corresponding to the timing set information.

5. A timing generator means comprising a plurality of N timing generators, N being an integer of 2 or greater than 2, each of the N timing generators including a clock generator, a period generator and a clock data processing circuit, said timing generator means being used in a semiconductor device testing apparatus which is arranged such that a timing of generation of a clock outputted from each of said clock generators is controlled based on data previously set in a memory provided in each of said clock generators, thereby to generate a clock at a desired timing from each of the clock generators, and the clock pulses thus generated are multiplexed to produce a test pattern signal for testing a semiconductor device using the multiplexed clock pulses, the clock data processing circuit of each of said N timing generators including:

a multiplier supplied with period data read out of period data memory of the associated clock data processing circuit, for multiplying a value of the supplied period data by N;

a subtracter having one input terminal supplied with the period data multiplied by N by said multiplier or the period data read out of the period data memory, and performing a subtraction between the period data multiplied by N and clock data supplied to the other input terminal of said subtracter from the outside;

selecting means for selecting one of the clock data supplied to said subtracter and a subtraction value outputted from an output terminal of said subtracter to output it to a memory provided in the associated clock generator;

first control means for controlling said selecting means so as to select the clock data supplied to said subtracter when a value of clock data is smaller than that of period data, thereby preventing a subtraction value outputted from the output terminal of said subtracter from being stored in the memory of the associated clock generator; and

second control means for supplying, only in the case that N or more period data are in succession, the period of each of said period data being a constant, period data read out of said period data memory to the associated multiplier to multiply the period data by N, thereby enabling the subtraction value outputted from the output terminal of the associated subtracter and a next flag outputted from a carry signal output terminal of the associated subtracter to be stored in the memory of the associated clock generator, said next flag representing that a clock is to be generated in the next cycle, and

whereby in the case of operating each timing generator in N way system, when clock data for generating a clock at a desired timing point in the next cycle is supplied together with period data read out of the associated period data memory, a next flag outputted from the carry signal output terminal of the associated subtracter and the subtraction value outputted from the output terminal of the associated subtracter can be stored in the memory of the associated clock generator.

6. The timing generator means according to claim 5, wherein

said first control means includes a gate having two input terminals and an output terminal one input terminal of which is connected to the carry signal output terminal of the associated subtracter, the other input terminal of which is connected to an inhibit signal supply terminal, and the output terminal of which is connected to a control terminal of the associated selecting means and the memory of the associated clock generator, and wherein

in the case of operating each timing generator in N way system, an inhibit signal is supplied to said the other input terminal of said gate through said inhibit signal supply terminal, thereby to prevent said selecting means from selectively outputting the subtraction value outputted from the output terminal of the associated subtracter as well as prevent said gate from passing the next flag outputted from the carry signal output terminal of the associated subtracter therethrough.

7. The timing generator means according to claim 5, wherein

said second control means includes a gate having two input terminals and an output terminal one input terminal of which is connected to the carry signal output terminal of the associated subtracter, the other input terminal of which is connected to an enabling signal supply terminal, and the output terminal of which is connected to a control terminal of the associated selecting means and the memory of the associated clock generator, and wherein

only in the case that N or more period data are in succession, the period of each of said period data being a constant, an enabling signal is supplied to said the other input terminal of said gate through said enabling signal supply terminal, thereby to enable said selecting means to selectively output the subtraction value outputted from the output terminal of the associated subtracter as well as enable said gate to pass the next flag outputted from the carry signal output terminal of the associated subtracter therethrough.

8. The timing generator means according to claim 5, wherein

said first control means and said second control means use a gate in common, said gate having two input terminals and an output terminal one input terminal of which is connected to the carry signal output terminal of the associated subtracter, the other input terminal of which is connected to an inhibit signal supply terminal and an enabling signal supply terminal, and the output terminal of which is connected to a control terminal of the associated selecting means and the memory of the associated clock generator, and wherein

in the case of operating each timing generator in N way system, an inhibit signal is supplied to said the other input terminal of said gate through said inhibit signal supply terminal, thereby to prevent said selecting means from selectively outputting the subtraction value outputted from the output terminal of the associated subtracter as well as prevent said gate from passing the next flag outputted from the carry signal output terminal of the associated subtracter therethrough, and

only in the case that N or more period data are in succession, the period of each of said period data being a constant, an enabling signal is supplied to said the other input terminal of said gate through said enabling signal supply terminal, thereby to enable said selecting means to selectively output the subtraction value outputted from the output terminal of the associated subtracter as well as enable said gate to pass the next flag outputted from the carry signal output terminal of the associated subtracter therethrough.

9. The timing generator means according to claim 5, wherein

said inhibit signal supply terminal and said enabling signal supply terminal are connected to said the other input terminal of said gate through an OR gate.

10. The timing generator means according to claim 8, wherein

said gate used in common by said first control means and said second control means is an AND gate, and wherein

said subtracter subtracts the clock data from the period data multiplied by N only in the case that N or more period data are in succession, the period of each of said period data being a constant, and when the result of the subtraction is a negative (minus) value, a next flag of logical H is outputted from the carry signal output terminal, and wherein

an inhibit signal of logical L is supplied to said inhibit signal supply terminal, and an enabling signal of logical H is supplied to said enabling signal supply terminal.

11. The timing generator means according to claim 5, wherein the period data memory of each of said clock data processing circuits has various kinds of period date previously set from a main controller, each of said subtracters performs a subtraction between period data read out of the associated period data memory or period data multiplied by N by the associated multiplier and clock data supplied from the main controller, and said next flag is outputted from the carry signal output terminal of the associated subtracter when a value of the clock data is greater than that of the period data multiplied by N.

12. The timing generator means according to claim 5, wherein there are provided short circuits each for bypassing the associated multiplier of said multipliers, and switching means each for turning on/off the associated short circuit of said short circuits, and wherein only in the case that N or more period data are in succession, the period of each of said period data being a constant, each of said switching means turns off the associated short circuit.

13. The timing generator means according to claim 5, wherein based on timing set information supplied from a pattern generator to the associated clock data processing circuit of said clock data processing circuits, period data is read out of the period data memory of the associated clock data processing circuit, said period data corresponding to the timing set information.