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Thin film transistor array panel and a method for manufacturing the same

  • US 6,255,130 B1
  • Filed: 09/07/1999
  • Issued: 07/03/2001
  • Est. Priority Date: 11/19/1998
  • Status: Expired due to Term
First Claim
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1. A method for manufacturing a thin film transistor array panel, comprising the steps of:

  • forming a gate wire including a gate line and a gate electrode connected to the gate line on an insulating substrate;

    forming a gate insulating layer covering the gate wire;

    forming a semiconductor pattern on the gate insulating layer;

    forming an ohmic contact layer pattern on the semiconductor pattern;

    forming a data wire including a source electrode and a drain electrode that are made of the same layer on the ohmic contact layer and separated from each other, and a data line connected to the source electrode; and

    forming a passivation layer covering the data wire, wherein the source electrode and the drain electrode are separated by a photolithography process using a photoresist pattern, and the photoresist pattern has a first portion having a first thickness and located at least between the source electrode and the drain electrode, a second portion having a second thickness thicker than the first thickness, and a third portion having a third thickness thinner than the first thickness.

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