Silicon on insulator circuit structure with extra narrow field transistors and method of forming same

• US 6,255,147 B1
• Filed: 01/31/2000
• Issued: 07/03/2001
• Est. Priority Date: 01/31/2000
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Buynoski, Matthew S.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): PERT, EVAN T
• Application Number:
  US09/494,997
• Time in Patent Office: 519 Days
• Field of Search: 438/149, 438/151, 438/163, 438/164, 438/424
• US Class Current: 438/164
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76275 Vertical isolation by bonding techniques
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795

Abstract

A method of forming a narrow circuit component on a silicon on insulator (SOI) substrate includes silicon on insulator (SOI) substrate including forming a mask over the surface of a device layer to define an island region surrounded by a peripheral trench region. The mask is trimmed to reduce the size of the island and increase the size of the peripheral trench region. The peripheral trench region is then etched to isolate the island and a circuit component is formed therein

Claims

1. A method of forming a narrow circuit component on a silicon on insulator wafer, comprising:

a) forming a mask with a length dimension and a width dimension over a silicon device layer to mask a device island region and expose a peripheral trench region;

b) trimming a trim region of the mask to decrease at least one of the length dimension and the width dimension; and

c) etching the peripheral trench region of the silicon device layer to isolate the island region.

2. The method of forming a narrow circuit component on a silicon on insulator wafer of claim 1, further including forming a silicon nitride layer between the mask and the silicon device layer and the step of etching further includes etching the silicon nitride layer.

3. The method of forming a narrow circuit component on a silicon on insulator wafer of claim 2, wherein the step of trimming includes eroding the trim region using a chemical selective between the mask and silicon nitride.

4. The method of forming a narrow circuit component on a silicon on insulator wafer of claim 3, further including filling the peripheral trench region with insulating silicon dioxide.

5. The method of forming a narrow circuit component of a silicon on insulator wafer of claim 4, further including forming a silicon on insulator field effect transistor in the island region.

6. The method of forming a narrow circuit component on a silicon on insulator wafer of claim 5, wherein the chemical selective between the mask and the silicon dioxide is oxygen/fluorine.

7. A method of forming a narrow circuit component on a silicon on insulator wafer, comprising:

a) forming a mask over a silicon device layer to mask a device island region and expose a peripheral trench region with a width dimension;

b) trimming a trim region of the mask to increase the width dimension of the peripheral trench region; and

c) etching the peripheral trench region of the silicon device layer to isolate the island region.

8. The method of forming a narrow circuit component on a silicon on insulator wafer of claim 7, further including forming a silicon nitride layer between the mask and the silicon device layer and the step of etching further includes etching the silicon nitride layer.

9. The method of forming a narrow circuit component on a silicon on insulator wafer of claim 8, wherein the step of trimming includes eroding the trim region using a chemical selective between the mask and silicon nitride.

10. The method of forming a narrow circuit component on a silicon on insulator wafer of claim 9, further including filling the peripheral trench region with insulating silicon dioxide.

11. The method of forming a narrow circuit component of a silicon on insulator wafer of claim 10, further including forming a silicon on insulator field effect transistor in the is land region.

12. The method of forming a narrow circuit component on a silicon on insulator wafer of claim 11, wherein the chemical selective between the mask and the silicon dioxide is oxygen/fluorine.