Process of manufacturing a vertical dynamic random access memory device

• US 6,255,158 B1
• Filed: 09/22/2000
• Issued: 07/03/2001
• Est. Priority Date: 08/16/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Furukawa, Toshiharu, Horak, David V., Radens, Carl J., Mandelman, Jack A., Rupp, Thomas S., Gruening, Ulrike
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US09/667,652
• Time in Patent Office: 284 Days
• Field of Search: 438/243-249, 438/386-392
• US Class Current: 438/243
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffision region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.

Claims

1. A process of manufacturing a vertical dynamic random access memory device comprising the steps of:

(a) providing a substrate having a top surface;

(b) etching a device trench into the substrate, the device trench having a sidewall, a lower portion, and an upper portion;

(c) forming a signal storage node in the lower portion of the device trench, the signal storage node having a storage node conductor;

(d) forming a signal transfer device in the upper portion of the device trench, the signal transfer device having a first diffusion region coupled to the storage node conductor and extending from the sidewall of the device trench into the substrate, a bit line diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent to the sidewall of the device trench, a channel region extending in the substrate from the first diffusion region to the bit line diffusion region, a gate insulator coating the sidewall of the device trench above the storage node conductor and adjacent the substrate, and a gate conductor filling the device trench;

(e) coupling a bit line conductor to the bit line diffusion region;

(f) self-aligning a wordline conductor formed upon the gate conductor with the sidewall of the device trench.

2. The process of manufacturing a dynamic random access memory device according to claim 1 further comprising the step of depositing a nitride layer upon the top surface of the substrate before step (b), and step (b) includes etching the device trench through the nitride layer and into the substrate, wherein step (d) includes forming the gate conductor by filling the device trench to a level above the top surface of the substrate and step (f) includes etching a wordline trench selective to nitride into the gate conductor and depositing the wordline conductor into the wordline trench.

3. The process of manufacturing a dynamic random access memory device according to claim 2 further comprising the step of forming an oxide layer upon the nitride layer and step (b) includes etching the device trench through the oxide layer, through the nitride layer, and into the substrate.

4. A process of manufacturing a vertical dynamic random access memory device comprising the steps of:

(a) providing a substrate having a top surface;

(b) depositing a nitride layer upon the top surface of the substrate;

(c) etching a device trench into the substrate, the device trench having a sidewall, a lower portion, and an upper portion;

(d) forming a signal storage node in the lower portion of the device trench, the signal storage node having a storage node conductor;

(e) coating the storage node conductor with a trench-top insulator;

(f) forming a signal transfer device in the upper portion of the device trench, the signal transfer device having a first diffusion region coupled to the storage node conductor and extending from the sidewall of the device trench into the substrate, a bit line diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent to the sidewall of the device trench, a channel region extending in the substrate from the first diffusion region to the bit line diffusion region, a gate insulator coating the sidewall of the device trench above the storage node conductor, and a gate conductor filling the device trench to a level above the top surface of the substrate;

(g) depositing a photoresist;

(h) patterning the photoresist to expose the gate conductor;

(i) etching the gate conductor selective to nitride to form a wordline trench aligned with the sidewall of the device trench; and

(j) depositing a wordline conductor in the wordline trench having a sidewall aligned with the sidewall of the device trench regardless of whether the photoresist is patterned in alignment with the sidewall of the device trench.

5. The process of manufacturing a dynamic random access memory device according to claim 4 further comprising the step of forming an oxide layer upon the nitride layer and wherein step (c) includes etching the device trench through the oxide layer, through the nitride layer, and into the substrate.