Semiconductor device with outwardly tapered sidewall spacers and method for forming same

• US 6,255,180 B1
• Filed: 05/01/2000
• Issued: 07/03/2001
• Est. Priority Date: 05/14/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Smith, Eugene C.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US09/565,292
• Time in Patent Office: 428 Days
• Field of Search: 438/172, 438/167, 438/585, 438/659, 438/260, 438/301, 438/303
• US Class Current: 438/301
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer

Abstract

The present invention advantageously provides a method for forming a nitride sidewall spacer having a relatively thin upper portion and a lower portion that increases in lateral thickness as it substantially tapers toward an underlying surface. In an embodiment, nitride sidewall spacers having this shape are formed upon the opposed sidewall surfaces of gate conductors which are dielectrically spaced above a semiconductor substrate. The upper portion of each spacer is bounded by a substantially vertical upper outer surface while the lower portion is bounded by a lower outer surface which is angled away from the upper outer surface. A unitary source/drain implant may be forwarded into the substrate to form graded junctions. The implant is self-aligned to the upper outer surfaces of the nitride spacers. As such, the graded junctions are displaced laterally from the gate conductors by a distance which is dictated by the lateral thickness of the upper portion of each spacer. The graded junctions include inner regions which are shallower than, and have a lower concentration of dopant than, outer regions spaced from the gate conductor by the lower portions of the spacers.

Claims

1. A method, comprising:

etching a portion of a dielectric adjacent to a spacer selectively relative to a layer immediately beneath the dielectric, said spacer comprising a nitride and being adjacent to a sidewall of a transistor gate structure, wherein the spacer includes a lower portion and an upper portion each having respective lower and upper outer surfaces, and the lower outer surface tapers away from the transistor gate structure by an angle greater than that by which the upper outer surface tapers away from the transistor gate structure; and

subsequently

etching at least part of the lower portion of the spacer.

2. The method of claim 1, wherein the upper outer surface extends from the top of the sidewall spacer and the lower outer surface extends from the upper outer surface to the bottom of the sidewall spacer, and the spacer tapers over substantially its entirety.

3. The method of claim 2, wherein said etching a portion of the spacer reduces the angle by which the lower outer surface tapers away from the transistor gate structure.

4. The method of claim 3, wherein the layer immediately beneath the dielectric is an etch stop layer arranged above the sidewall spacer and a junction region of a semiconductor substrate, and said etching a portion of the dielectric comprises etching the dielectric selectively relative to the etch stop layer.

5. The method of claim 4, wherein the dielectric comprises silicon dioxide and the etch stop layer comprises silicon nitride, and wherein said etching a portion of the dielectric further comprises etching the dielectric using an etching technique selective to silicon dioxide over silicon nitride.

6. The method of claim 5, wherein said etching a portion of the sidewall spacer comprises etching a portion of the etch stop layer using an etching technique selective to silicon nitride over silicon.

7. The method of claim 2, wherein after said etching a portion of the sidewall spacer is complete, a portion of the sidewall spacer remains adjacent to the transistor gate structure.

8. The method of claim 2, wherein said etching a portion of the dielectric exposes a portion of the layer immediately beneath the dielectric.

9. The method of claim 2, further comprising prior to said removing a portion of an dielectric:

blanket depositing a spacer dielectric layer upon the transistor gate structure, wherein the transistor gate structure is dielectrically spaced above the semiconductor substrate; and

exposing the spacer dielectric layer to a carbon-based etchant to form the sidewall spacer.

10. The method of claim 9, wherein the spacer dielectric layer comprises silicon nitride, wherein said exposing comprises etching the spacer dielectric layer using a plasma provided with CHF₃ and C₂F₆, and wherein the plasma is absent externally supplied O_2.

11. The method of claim 9, wherein said etching the spacer dielectric layer while exposing the spacer dielectric layer to a carbon-based etchant causes a carbon-containing passivant to deposit across the spacer dielectric layer.

12. The method of claim 9, further comprising forming the dielectric above the transistor gate structure subsequent to said exposing the spacer dielectric layer to a carbon-based etchant.

13. The method of claim 9, wherein the sidewall spacer is formed such that the lower portion increases in thickness as it approaches the substrate and the upper portion has a substantially uniform thickness, and further comprising forwarding a source/drain implant into the substrate self-aligned to the upper outer surface of the sidewall spacers, thereby forming a graded junction within the substrate laterally spaced from the transistor gate structure.

14. The method of claim 13, wherein the graded junction comprises an inner portion arranged underneath the sidewall spacers and an outer portion laterally adjacent to the inner portion, and wherein a first concentration of dopant within the outer region is substantially greater than a second concentration of dopant within the inner region.

15. A method, comprising:

forming an dielectric above a pair of adjacent transistor gate structures dielectrically spaced above a semiconductor substrate, wherein sidewall spacers comprising silicon nitride are arranged adjacent the sidewalls of each of the transistor gate structures, wherein the sidewall spacers each include lower portions and upper portions having lower and upper outer surfaces, respectively, and wherein, for each of the sidewall spacers, the upper outer surface extends from the top of the sidewall spacer, the lower outer surface extends from the upper outer surface to the bottom of the sidewall spacer, and the lower outer surface tapers away from the transistor gate structure by an angle greater than that by which the upper outer surface tapers away from the structure and tapers over substantially its entirety;

etching a portion of the dielectric above a mutual graded junction arranged within the semiconductor substrate between the pair of adjacent transistor gate structures and at least partially beneath a sidewall spacer of each of the pair of adjacent transistor gate structures, wherein said etching a portion of the dielectric etches the dielectric selectively relative to a layer immediately beneath the dielectric; and

subsequently

etching at least part of the lower portions of the sidewall spacers adjacent to the mutual graded junction.

16. The method of claim 15, wherein said etching at least part of the lower portions reduces the angle by which the lower outer surfaces of the sidewall spacers adjacent to the mutual graded junction taper away from the transistor gate structure.

17. The method of claim 16, wherein after said etching at least part of the lower portions of the sidewall spacers adjacent to the mutual graded junction, the lower outer surfaces adjacent to the mutual graded junction taper away from the transistor gate structure by an angle less than the lower outer surfaces distal from the mutual graded junction.

18. The method of claim 15, wherein the mutual graded junction comprises inner portions arranged underneath a portion of the sidewall spacers of each of the transistor gate structures and an outer portion laterally adjacent to the inner portions, and wherein a first concentration of dopant within the outer region is substantially greater than a second concentration of dopant within the inner regions.

19. The method of claim 18, wherein the layer immediately beneath the dielectric is an etch stop layer arranged above the sidewall spacer and the mutual graded junction, and wherein said etching a portion of the dielectric comprises etching the dielectric selectively relative to a material within the etch stop layer.

20. The method of claim 19, wherein the dielectric comprises silicon dioxide and etch stop layer comprises silicon nitride, and wherein said etching a portion of the dielectric further comprises etching the dielectric using an etch technique selective to silicon dioxide over silicon nitride.