Method for forming a semiconductor device

• US 6,255,204 B1
• Filed: 05/21/1999
• Issued: 07/03/2001
• Est. Priority Date: 05/21/1999
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Adetutu, Olubunmi O., Tobin, Philip J., Maiti, Bikas, Hegde, Rama I.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/316,012
• Time in Patent Office: 774 Days
• Field of Search: 438/585, 438/589, 438/592, 438/631, 438/633-634, 438/628, 438/636, 438/637, 438/656, 438/660, 438/663, 438/669, 438/688, 438/675, 438/627, 438/643, 438/653, 438/957, 257/751
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

A first metal-containing material (22) is formed over a semiconductor device substrate (10). A second metal-containing material (32) is formed over the first metal containing material (22). The combination of the second metal-containing material (32) formed over the first metal-containing material (22) forms a metal stack (34). The metal stack (34) is annealed and a post-anneal stress of the metal stack (34) is less than an individual post-anneal stress of either one of the first conductive film (22) or the second conductive film (32).

Claims

1. A method for forming a semiconductor device comprising:

forming a first metal-containing layer over a substrate, wherein the first metal-containing layer has a first pre-anneal compressive/tensile stress;

forming a source region, a drain region and a channel between the source region and the drain region, wherein at least a portion of the channel is under the first metal-containing layer;

forming a second metal-containing layer over the first metal-containing layer, wherein the second metal-containing layer has a second pre-anneal compressive/tensile stress, and wherein a combination of at least the second metal-containing layer over the first metal-containing layer forms a gate electrode stack; and

annealing the gate electrode stack, wherein a composite post-anneal compressive/tensile stress of the gate electrode stack is less than an individual post-anneal compressive/tensile stress of either one of a separately annealed first metal-containing layer and a separately annealed second metal-containing layer.

2. The method of claim 1, wherein the first metal-containing layer includes titanium nitride.

3. The method of claim 1, wherein the first metal-containing layer includes a material selected from a group consisting of tungsten, tantalum, molybdenum, zirconium, and aluminum.

4. The method of claim 1, wherein forming the first metal-containing layer includes using a first deposition method, and wherein forming the second metal-containing layer includes using a second deposition method, wherein the first deposition method is a different deposition method than the second deposition method.

5. The method of claim 4, wherein the first deposition method includes a thermal chemical vapor deposition method.

6. The method of claim 1, wherein the individual post-anneal compressive/tensile stress of the first metal-containing layer is greater than approximately 500 megapascals.

7. The method of claim 1, wherein the second metal-containing layer includes titanium nitride.

8. The method of claim 1, wherein the second metal-containing layer comprises a material selected from a group consisting of tungsten, tantalum, molybdenum, zirconium, and aluminum.

9. The method of claim 1, wherein an individual post-anneal compressive/tensile stress of the second metal-containing material is greater than approximately 500 megapascals.

10. The method of claim 1, wherein the gate electrode stack is an inlaid gate electrode stack.

11. The method of claim 1, wherein annealing the gate electrode stack includes a furnace annealing process performed at a temperature in a range of approximately 700-950°

C. and for a time in a range of approximately 5-30 minutes.

12. The method of claim 1, wherein annealing the gate electrode stack includes a rapid thermal annealing process performed at a temperature in a range of approximately 700-1100°

C. and for a time less than approximately 1 minute.

13. The method of claim 1, wherein the post-anneal compressive/tensile stress of the gate electrode stack is less than approximately 800 megapascals.

14. The method of claim 1, further comprising forming a third metal-containing layer over the second meal-containing layer, wherein the post-anneal compressive/tensile stress of the rate electrode stack is less than a post-anneal compressive/tensile stress of the third metal-containing layer.

15. The method of claim 1, wherein forming the first metal-containing layer and forming the second metal-containing layer are performed using a same processing platform during a single evacuation cycle.

16. A method for forming a semiconductor device comprising:

forming a first dielectric layer over a substrate;

forming an opening in the first dielectric layer;

forming a first metal-containing layer within the opening;

forming a source region a drain region and a channel between the source region and the drain region, wherein at least a portion of the channel is under the first metal-containing layer;

forming a second metal-containing layer over the first metal-containing material, wherein a combination of the second metal-containing layer over the first metal-containing layer forms a portion of a gate electrode stack, and wherein a composite compressive/tensile stress of the portion of the gate electrode stack is less than an individual compressive/tensile stress of either one of the first metal-containing layer and the second metal-containing layer; and

removing portions of the second metal-containing material and the first metal-containing material lying outside of the opening to form and inlaid gate electrode structure.

17. The method of claim 16, wherein the first metal-containing layer includes a material selected from a group consisting of titanium, tungsten, tantalum, molybdenum, zirconium, and aluminum.

18. The method of claim 16, wherein the second metal-containing layer includes a material selected from a group consisting of titanium, tungsten, tantalum, molybdenum, zirconium, and aluminum.

19. The method of claim 16, wherein at least one of the first metal-containing layer and the second metal-containing layer is formed using a process selected from a group consisting of physical vapor deposition, thermal chemical vapor deposition, and plasma enhanced chemical vapor deposition.