Dynamic random access memory

• US 6,255,683 B1
• Filed: 12/29/1998
• Issued: 07/03/2001
• Est. Priority Date: 12/29/1998
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG), International Business Machines Corporation
• Original Assignee: Infineon Technologies AG, International Business Machines SA (International Business Machines Corporation)
• Inventors: Radens, Carl, DeBrosse, John, Mandelman, Jack, Gruening, Ulrike
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/222,391
• Time in Patent Office: 917 Days
• Field of Search: 257/296, 257/309, 257/330, 257/301, 257/315, 257/333, 257/298, 257/513, 257/302, 257/300, 438/717, 438/258, 438/253, 438/242, 438/147, 438/386, 438/735, 438/388
• US Class Current: 257/301
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A memory cell formed in a semiconductor body includes a vertical trench with a polysilicon fill as a storage capacitor and a field effect transistor having a source formed in the sidewall of the trench, a drain formed in the semiconductor body and having a surface common with a top surface of the semiconductor body, and having a channel region that includes both vertical and horizontal portions and a polysilicon gate that is in an upper portion of the trench. A process for fabrication provides an insulating oxide layer at the top of the polysilicon fill portion that serves as the storage node and the polysilicon fill portion that serves as the gate conductor.

Claims

1. A memory cell for use in a dynamic random access memory of the kind that uses a transistor and a storage capacitor in a semiconductor body comprising:

a relatively deep trench with substantially, vertical side walls that includes a deep portion that is filled with doped polysilicon, that is insulated from the semiconductor body by a dielectric layer and that serves as the storage node of the memory cell, the polysilicon fill also including an oxide layer at its top; and

a transistor that includes a drain region that is part of the semiconductor body and a source region that lies in the semiconductor body along a sidewall at top of the polysilicon fill of the deeper portion of the trench, and a channel region extending between the source and drain regions along the top surface of the semiconductor body and along a sidewall of the deep trench that includes vertical and horizontal portions, and a doped silicon gate conductor that fills the upper portion of the trench and is electrically insulated from the doped polysilicon in the deeper portion of the trench both by a dielectric layer that was formed at the top of the polysilicon fill in the deeper portion of the trench and a dielectric layer that was formed as part of the gate dielectric of the transistor.

2. A memory cell for use in a dynamic random access memory of the kind that uses a transistor and a storage capacitor in a semiconductor body comprising:

a relatively deep trench with substantially vertical side walls that includes a deep portion that is filled with doped polysilicon, that is insulated from the semiconductor body by a first and second dielectric layers;

the first dielectric layer lining sidewalls of an upper portion of the deep portion of the trench, and the second dielectric layer lining sidewalls of a lower portion of the deep portion of the trench and lining a surface of the first dielectric layer;

the doped polysilicon having a thermally formed oxide layer at on a top surface thereof;

a transistor that includes a drain region that is part of the semiconductor body and a source region that lies in the semiconductor body along a sidewall at the top of the polysilicon fill of the deeper portion of the trench, and a channel region extending between the source and drain regions along the top surface of the semiconductor body and along a sidewall of the deep trench that includes vertical and horizontal portions, and a doped silicon gate conductor that fills the upper portion of the trench and is electrically insulated from the doped polysilicon in the deeper portion of the trench both by the thermally formed oxide layer that was formed at the top of the polysilicon fill in the deeper portion of the trench and a third dielectric layer that was formed as part of the gate dielectric of the transistor; and

a strap at the top of the polysilicon fill of the deeper portion of the trench which connects the polysilicon fill to the source region, the strap extending to contact the gate dielectric.