DRAM cell configuration and method for its production

• US 6,255,684 B1
• Filed: 05/04/1998
• Issued: 07/03/2001
• Est. Priority Date: 05/02/1997
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Roesner, Wolfgang, Hofmann, Franz, Risch, Lothar
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Owens, Douglas W.
• Application Number:
  US09/071,798
• Time in Patent Office: 1,156 Days
• Field of Search: 257/302, 257/301, 257/304, 257/305, 438/242, 438/241, 438/270
• US Class Current: 257/302
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks, with a memory cell area of 4 F². F is a minimum structure size which can be produced by using the respective technology.

Claims

1. A DRAM cell configuration, comprising:

a substrate of semiconductor material;

memory cells each including a read-out transistor integrated in said substrate as a vertical MOS transistor, and a storage capacitor having a storage node;

a bit line and a word line;

said vertical MOS transistor having a gate electrode, two first source/drain regions, and two second source/drain regions;

said first source/drain regions disposed separately one after the other along said bit line, adjoining said bit line and each of said two first source/drain regions belonging to a further, adjacent vertical MOS transistor; and

said second source/drain regions connected to said storage node;

a gate oxide adjoining exactly two opposite sides of said gate electrode;

two channel regions each adjoining said gate oxide;

said gate electrode disposed between said two channel regions;

said gate electrodes of adjacent vertical MOS transistors along said word line connected to one another; and

said gate electrode and said storage node disposed one under the other.

2. The DRAM cell configuration according to claim 1, wherein said storage capacitor has a capacitor dielectric, and at least part of said capacitor dielectric is disposed radially further outward, relative to a vertical axis running through said gate electrode, than part of said storage node adjoining it.

3. The DRAM cell configuration according to claim 1, including a trench in which said gate electrode and said storage node are disposed.

4. The DRAM cell configuration according to claim 1, wherein said substrate has a surface, said gate electrode has a cross-section parallel to said surface, said storage node has a cross-section parallel to said surface, and dimensions of said cross-section of said gate electrode substantially are congruent to dimensions of said cross-section of said storage node.

5. The DRAM cell configuration according to claim 4, wherein:

said storage node is disposed underneath said gate electrode;

said storage node has sides parallel to said word line and sides parallel to said bit line;

said storage capacitor has a capacitor dielectric, part of said capacitor dielectric is disposed on said sides parallel to said word line and is interrupted for connecting said storage node to said second source/drain regions; and

insulating material is disposed on said sides parallel to said bit line and encompasses a different part of said capacitor dielectric.

6. The DRAM cell configuration according to claim 1, wherein said bit line runs above said word line, and said word line is disposed at a level of said gate electrode.

7. The DRAM cell configuration according to claim 1, wherein said first and second source/drain regions are doped regions in said substrate;

and said bit line and said word line contain at least one material selected from the group consisting of polysilicon, metal silicide and tungsten.