DRAM cell configuration and method for its production
First Claim
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1. A DRAM cell configuration, comprising:
- a substrate of semiconductor material;
memory cells each including a read-out transistor integrated in said substrate as a vertical MOS transistor, and a storage capacitor having a storage node;
a bit line and a word line;
said vertical MOS transistor having a gate electrode, two first source/drain regions, and two second source/drain regions;
said first source/drain regions disposed separately one after the other along said bit line, adjoining said bit line and each of said two first source/drain regions belonging to a further, adjacent vertical MOS transistor; and
said second source/drain regions connected to said storage node;
a gate oxide adjoining exactly two opposite sides of said gate electrode;
two channel regions each adjoining said gate oxide;
said gate electrode disposed between said two channel regions;
said gate electrodes of adjacent vertical MOS transistors along said word line connected to one another; and
said gate electrode and said storage node disposed one under the other.
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Abstract
A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks, with a memory cell area of 4 F2. F is a minimum structure size which can be produced by using the respective technology.
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Citations
7 Claims
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1. A DRAM cell configuration, comprising:
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a substrate of semiconductor material;
memory cells each including a read-out transistor integrated in said substrate as a vertical MOS transistor, and a storage capacitor having a storage node;
a bit line and a word line;
said vertical MOS transistor having a gate electrode, two first source/drain regions, and two second source/drain regions;
said first source/drain regions disposed separately one after the other along said bit line, adjoining said bit line and each of said two first source/drain regions belonging to a further, adjacent vertical MOS transistor; and
said second source/drain regions connected to said storage node;
a gate oxide adjoining exactly two opposite sides of said gate electrode;
two channel regions each adjoining said gate oxide;
said gate electrode disposed between said two channel regions;
said gate electrodes of adjacent vertical MOS transistors along said word line connected to one another; and
said gate electrode and said storage node disposed one under the other. - View Dependent Claims (2, 3, 4, 5, 6, 7)
said storage node is disposed underneath said gate electrode;
said storage node has sides parallel to said word line and sides parallel to said bit line;
said storage capacitor has a capacitor dielectric, part of said capacitor dielectric is disposed on said sides parallel to said word line and is interrupted for connecting said storage node to said second source/drain regions; and
insulating material is disposed on said sides parallel to said bit line and encompasses a different part of said capacitor dielectric.
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6. The DRAM cell configuration according to claim 1, wherein said bit line runs above said word line, and said word line is disposed at a level of said gate electrode.
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7. The DRAM cell configuration according to claim 1, wherein said first and second source/drain regions are doped regions in said substrate;
- and said bit line and said word line contain at least one material selected from the group consisting of polysilicon, metal silicide and tungsten.
Specification